Sahada programlanabilir kapı dizileri ile lojik devre tasarımı ve VHDL kullanılarak bazı devrelerin gerçekleştirilmesi
Başlık çevirisi mevcut değil.
- Tez No: 75488
- Danışmanlar: PROF. DR. AHMET DERVİŞOĞLU
- Tez Türü: Yüksek Lisans
- Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
- Anahtar Kelimeler: Belirtilmemiş.
- Yıl: 1998
- Dil: Türkçe
- Üniversite: İstanbul Teknik Üniversitesi
- Enstitü: Fen Bilimleri Enstitüsü
- Ana Bilim Dalı: Elektronik ve Haberleşme Mühendisliği Ana Bilim Dalı
- Bilim Dalı: Belirtilmemiş.
- Sayfa Sayısı: 112
Özet
ÖZET SAHADA PROGRAMLANABİLİR KAPI DİZİLERİ İLE LO JİK DEVRE TASARIMI VE BAZI DEVRELERİN VHDL YARDIMI İLE GERÇEKLEŞTİRİLMESİ Bu çalışmada FPGA kullanılarak lojik devre tasarımının nasıl gerçekleştirilebileceği incelenmiştir. Çalışma genelde teorik ve pratik olarak ikiye ayrılmıştır. Teorik kısımda FPGA kullanılarak lojik devre sentezi konusu incelenmiş ve bu konunun geliştirilmesine yönelik çalışmalar gerçekleştirilmiştir. Pratik kısımda ise FPGA tasarımının mevcut araçlar kullanılarak, yüksek seviyede tasarım yöntemi ile gerçekleştirilmesine yönelik bir kaynak olması amacıyla VHDL kullanılarak FPGA yardımıyla bazı lojik devre tasarımları gerçekleştirilmiştir. Çalışmanın ilk bölümünde, günümüzde FPGA teknolojisinin devre tasarımına getirdiği avantajlar verilmiştir. İkinci bölümde ise günümüzde kullanılan FPGA teknolojileri ve FPGA üreten şirketlerin ürünleri incelenmiş ve bu ürünler arasında bir karşılaştırma yapılmıştır. Çalışmanın üçüncü bölümünde doğruluk tablosu (look-up table, LUT) yapısındaki FPGA'ler kullanılarak Boole fonksiyonlarının gerçekleştirilmesine yönelik“mis- fpga”yöntemi incelenmiştir. Bu yöntemde fonksiyonel ayrıştırmanın geliştirilmesine yönelik bir çalışma gerçekleştirilmiş ve bu çalışma bir bilgisayar programı (ESB) haline getirilerek“mis-fpga”yöntemi içerisinde kullanılmasının avantajlarıaçıklanmıştır. Üçüncü bölümde ayrıca, geliştirilen programın karmaşıklık mertebesi de verilmiştir. Dördüncü bölümde VHDL ve FPGA kullanılarak lojik devre tasanmı akışı incelenmiş ve bu akış kullanılarak bazı lojik devre tasarım örnekleri gerçeklenmiştir. Beşinci ve son bölümde, elde edilen sonuçlar ve ileriye yönelik yapılabilecek çalışmalar verilmektedir. xı
Özet (Çeviri)
SUMMARY DIGITAL DESIGN BY FIELD PROGRAMMABLE GATE ARRAYS AND SOME CIRCUIT REALIZATIONS USING VHDL Microelectronics has been the enabling technology for the development of hardware and software systems in the recent decades. The continuously increasing level of integration of electronic devices on a single substrate has led to the fabrication of increasingly complex systems. The integrated circuit technology, based upon the use of semiconductor materials, has progressed tremendously. While a handful of devices were integrated on the first circuits in the 1960s, circuits with over one million devices have been successfully manufactured in the late 1980s. Such circuits are often called Very Large Scale Integration (VLSI) or microelectronic circuits. Designing increasingly integrated and complex circuits requires a larger and larger capital invesment, due to the cost of refining the precision of the manufacturing process so that finer and finer devices can be implemented. Similarly, the growth in scale of the circuits requires larger efforts in achieving zero-defect designs. The economics of VLSI circuits relies on the principle that replicating a circuit is straightforward and therefore the design and manufacturing costs can be recovered over a large volume of sales. The trend toward higher integration is economically positive because it leads to a reduction in the number of components per system, and therefore to a reduced cost in packaging and interconnection, as well as to a higher reliability of the overall system. More importantly, higher integration correlates to faster circuits, because of the reduction of parasitic effects in the electronic devices xnthemselves and in the interconnections. As a result, the higher the integration level is, the better and cheaper the final product results. At present, many electronic systems require integrated dedicated components that are specialized to perform a task or a limited set of tasks. These are called Application Specific Integrated Circuits, or ASICs, and occupy a large portion of the market share. Some circuits in this class may not be produced in large volume because of the specificity of their application. Thus other factors are important in microelectronic circuit economics. First, the use of particular design styles according to the projected volume of sales. Second, the reduction of design time, which has two implications. A reduction of design cost, and a reduction of the time-to-market. This last factor has been shown to be key to the profitability of many applications. Third, the quality of the circuit design and fabrication, measured in performance and manufacturing yield. As the investment made in any chip design is significant, designers search for ways in which to amortise the design effort over a large number of devices. This might result from a huge single market for one device or, more probably, multiple smaller markets for a more adaptable device. It is crucial for a company to have its product hit the market first. This is in accordance with a cardinal principle of the 20th century economies that whoever enters the market first (with the right product) captures it for the first few years at least, when most of the profit is to be made. It becomes critical then to minimize the design-manufacture-test cycle time. One way of doing so is to use programmable hardware. The components of this hardware (logic blocks and interconnect) lie uncommitted on an already fabricated chip and can be programmed by the user to implement any kind of digital circuit. This methodology eliminates manufacturing/mask process from the design process. In fact, chip fabrication is removed from the cycle, reducing the cycle time from months to hours. As a solution xuiof these requirement, programmable logic arrays have been introduced, among which Field Programmable Gate Arrays (FPGA's) are the most promising. The Field Programmable Gate Array or FPGA as it is more widely called is a type of programmable device. Programmable devices are a class of general-purpose chips that can be configured for a wide variety of applications. The first programmable device, which achieved a widespread use, was the PROM (Programmable Read-Only Memory). PROMs, a one-time programmable device comes in two basic versions: 1) The Mask-Programmable Chip, programmed only by the manufacturer, 2) The Field- Programmable Chip, programmed by the end-user. The Field Programmable PROM developed into two types, the Erasable Programmable Read-Only Memory (EPROM) and the Electrically Erasable Programmable Read-Only Memory (EEPROM). The EEPROM has the advantage of being erasable and reprogrammable many times. Another step took place in this field, which lead to the development of the Programmable Logic Device (PLD). These devices were constructed to implement logic circuits. The PLD included an array AND gates connect to an array of OR gates. The PAL (Programmable Array Logic) is a commonly used PLD consisting of a programmable AND-plane followed by a fixed OR-plane. PALs come in both mask and field versions. The PAL was designed for small logic circuits. The Mask-Programmable Gate Array (MPGA) was developed to handled larger logic circuits. A common MPGA consists of rows of transistors that can be interconnected to implement desired logic circuits. User specified connects are available both within the rows and between the rows. This enabled implementation of basic logic gates and the ability to interconnect the gates. As the metal layers are defined at the manufacturer, significant time and cost are incurred in producing the run. In 1985, Xilinx Inc. introduced the FPGA (Field Programmable Gate Array). The interconnects between all the elements were designed to be user programmable. xivField programmable logic and in particular, field programmable arrays, have become the solution of choice for logic design implementation in applications where time to market is a critical product development factor. In addition, reconfigurable arrays have been used to enhance customer product flexibility in ways that no other technology can match. Microprocessors have traditionally been used to satisfy time to market and end product flexibility needs. This solution may not meet performance constraints. Typical design processes, therefore, reach a point where the overall design is partitioned into hardware and software components. An interface is defined and the design process continues along two parallel paths. Sometime later, the software and hardware components must be integrated. Problems usually develop at this point because of interface misinterpretation or partitioning that cannot meet design requirements. This impacts the hardware, the software and the schedule. If the hardware design is realized in programmable logic, the hardware can be manipulated as easily as the software. Products which adapt to the end users particular requirements through self directed or end user directed reconfiguration are becoming more prevalent. As the number of modes of operation increases, mode specific hardware becomes a less cost-effective solution. In the case where the end user is truly directing the adaptation, predetermined hardware solutions become untenable. Reconfigurable logic enables design solutions where dynamic hardware-software repartitioning is possible. Programmable logic not only vastly improves the time necessary to implement a static design, but significant time to market and product feature benefits can be realized when hardware can be dynamically altered as easily as software. To reduce design cycles, designers have also turned towards high-level design languages and logic synthesis tools. Many programmable logic solutions are poorly suited to this design methodology, however. An incompatibility exists between logic synthesis algorithms originally developed for gate level design and the block-like xvstructures found on many programmable logic devices. This can result in significant under utilization or degraded performance. In either case a more expensive device is required. Real gate level programmable devices are ideally suited to this design methodology. When schematic based design methods are used, some programmable logic solutions impose significant constraints on design implementation to insure satisfactory results. This imposition tends to bind the design to a particular programmable device and requires a significant learning investment. Any design specification changes which impact design decisions made to fit this imposed structure can have disastrous effects on utilization and performance and potentially require a more expensive device or even a costly redesign. Gate level programmable devices coupled with sophisticated, timing driven, implementation tools minimize device specific optimization. The design of digital systems, especially VLSI systems, is divided into the following steps:. Design Specification: The desired behavior of the system is specified at some level of abstraction.. High-level Design: This stage transforms the design specification into a description that uses memories, adders, register files, controllers, etc. This description is called the register-transfer level or RTL, description.. Logic Design: The RTL implementation is first optimized for an objective function, such as minimum chip area, meeting the performance constraints, low power, etc. This step is called logic optimization. The optimized representation is then mapped to some primitive cells present in a library. This final implementation is in terms of interconnections of gates, functional units, and registers.. Physical Design: The locations of various modules on the chip are determined (placement), and the interconnections of the circuit are routed between or through the placed modules. Also, the pad locations for inputs and outputs are determined in this step. The final layout is sent for fabrication. xviThe subject matter of this thesis is based on the logic synthesis using FPGAs, which is the third step of the above flow. Logic synthesis takes the circuit description at the register-transfer level and generates an optimal implementation in terms of an interconnection of logic gates. User programmable or field-programmable hardware devices are prefabricated as arrays of identical programmable logic blocks with routing resources, and are configured by the user into the desired circuit functionality. The configuration (or programming) time is small - of the order of minutes. Consequently, turnaround time is much smaller. This makes them attractive for rapid system prototyping. Also, being off-shelf components, they provide a cheaper alternative to mask - programmable gate arrays (MPGAs) for low-volume applications. Although MPGAs provide significant performance benefits, they do not offer the flexibility of user- programmability, and the manufacturing time is still a bottleneck. A sub-class of user-programmable devices is the reprogrammable devices - those that can be programmed any number of times. Reprogrammability reduces the overhead for making design changes, since the same device can be reused. Broadly speaking, the user-programmable devices can be classified into two categories:. Programmable logic devices (PLDs), and. Field-programmable gate arrays (FPGAs) PLDs are typically interconnections of programmable logic arrays (PLAs). A PLA has two planes - an AND planeand an OR plane. The AND plane implements the product terms and the OR plane realizes their OR. Thus they implement a sum-of- products representation of the logic function. Both the AND and the OR planes are programmable. In general, a PLA can have more than one output. Some PLD architectures are also based on programmable array logic (PAL). A PAL is like a PLA except that the connections to the OR plane are fixed. Commonly used PLD architectures are those offered by A.M.D. and Altera. One disadvantage of PLDs is xvnthat since they implement sum-of-products representation, functions with large number of product terms cannot be efficiently implemented. FPGAs are like MPGAs in that they have uncommitted logic blocks and interconnect. However, they are completely user-programmable and in this regard are like PLDs. FPGAs differ from PLDs in the logic block granularity; FPGAs have more fine-grain logic blocks or gates. There are two popular categories of FPGA block structures, namely Look-Up Table-based (LUT) and multiplexor-based; the resulting architectures are called LUT-based and MUX-based architectures, respectively. The first chapter of this thesis is the introduction part, which gives an overview to the FPGAs and introduces its place in the top-down design methodology. Second chapter is based on the general subjects related to FPGAs like architectures, programming technologies, realising Boolean functions using LUT-based FPGAs and details of a technology mapping algorithm called“mis-fpga”. Chapter three is focused on a decomposition method called functional decomposition that is based on Roth-Karp decomposition. A computer program has been developed for the investigation of the estimation of minimum column multiplicity method that is given in [5]. In chapter four, a comparison of the VHDL design entry and conventional schematic based entry when using FPGAs has been given. Furthermore, three digital circuit designs have been given using the top-down design methodology with VHDL and FPGA. Those circuits have been realized using a Xilinx 3100A family FPGA, in order to be used as a lab exercise in“Logic Circuits Laboratory”course. Conclusions and farther problems are given in chapter 5. xvin
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