Effects of random delay errors in transversal filters
Başlık çevirisi mevcut değil.
- Tez No: 402870
- Danışmanlar: PROF. MURAT TORLAK
- Tez Türü: Yüksek Lisans
- Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
- Anahtar Kelimeler: Belirtilmemiş.
- Yıl: 2011
- Dil: İngilizce
- Üniversite: The University of Texas at Dallas
- Enstitü: Yurtdışı Enstitü
- Ana Bilim Dalı: Belirtilmemiş.
- Bilim Dalı: Belirtilmemiş.
- Sayfa Sayısı: 67
Özet
Özet yok.
Özet (Çeviri)
Analog structures give the opportunity to design the nite impulse response (FIR) lters without analog-to-digital (AD) and digital-to-analog (DA) converters. By eliminating AD and DA converters, the lter will be faster, use less power, and occupy less area. An FIR lter consists of two main building components: the unit delay and linearly weighted combiner including lter coecients and the summer. The coecients of analog FIR lters in integrated circuits are generated by switched-capacitor or switched-current techniques using reliable Metal Oxide Semiconductor (MOS) capacitor and switches. Although the analog circuits are more sensitive to voltage and environment changes, these issues can be overcome by means of voltage reference and band gap reference circuits. On the other hand, the mismatches due to the fabrication process are inevitable. Accuracy of typical MOS structures is a ected by the errors inherent to the fabrication parameters such as global edge variations, oxide variations and carrier mobility variations. The e ects of coecient inaccuracies in transversal lters have been extensively investigated in the literature [1],[2]. However, the inaccuracies of implementing the unit delays have not received similar attention. The reason could be attributed to the fact that most implementations use fully digital structure where the delay can be implemented with very small jitter. This thesis analyzes the inaccuracies of the unit delay blocks in transversal lters and nds the statistical performance bounds of transversal lters under such inaccuracies. Delay elements can be implemented with switched-capacitor and analog delay lines, such as inverter chains and RC circuits. An inverter based delay element is considered to analyze the e ects of error in delay due to fabrication processes. Since the signal pass through the delay elements, the error in a delay element will also a ect the output of subsequent delay elements. The e ect of the delay inaccuracies to the lter response is frequency dependent because the delay will produce a shift in time domain but it appears as a frequency dependent phase shift (ejwt0) in frequency domain. Our analysis shows that the error in delay will be more pronounced in stop band frequencies.
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