Developing variation aware simulation tools, models, and designs for STT-RAM
Başlık çevirisi mevcut değil.
- Tez No: 523368
- Danışmanlar: DOÇ. Dr. YIRAN CHEN
- Tez Türü: Doktora
- Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
- Anahtar Kelimeler: Belirtilmemiş.
- Yıl: 2017
- Dil: İngilizce
- Üniversite: University of Pittsburgh
- Enstitü: Yurtdışı Enstitü
- Ana Bilim Dalı: Belirtilmemiş.
- Bilim Dalı: Belirtilmemiş.
- Sayfa Sayısı: 80
Özet
Özet yok.
Özet (Çeviri)
Technology scaling imposes many challenges on design and manufacturing of conventional memories, such as high leakage and reliability issues of SRAM, DRAM, and NAND flash. Extensive research has been performed to develop new memory technologies that can overcome these challenges, including phase-change memory (PCM), resistive memory (ReRAM), spin-transfer torque random access memory (STT-RAM), etc. Among all these technologies, STT-RAM is particularly identified as a potential replacement of DRAM in future main memory application because of its many attractive features like zero standby power, excellent CMOS-compatibility, etc. However, like all other memory technologies, STT-RAM has some problems, such as long switching time and large programming energy, being lack of a variation aware simulation tool which are waiting to be solved. In order to solve long switching time and large programming energy problems, Spin-Hall Effect (SHE) assisted STT-RAM structure (SHE-RAM) has been recently invented. In this work, I propose two possible SHE-RAM designs from the aspects of two different write access operations, namely, High Density SHE-RAM and Disturbance Free SHERAM, respectively. In addition to the SHE-RAM designs, I will also propose a simulation tool for STT-RAMs. As an early-stage modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. I will introduce a new member of NVSim family – NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption. In this work, I also developed a dynamic macromagnetic model for biaxial MTJ for MLC-STT circuit designs. Besides simulating the relations between the switching current and the switching time of each MTJ resistance state, this model is also capable to capture the switching transience that can be used to calculate the write error rate of the MLC-STT cell. Write performance and energy consumption of the MLC-STT cell can also be derived and optimized based on the model for different design configurations. Finally, this model allows designers to perform a comprehensive reliability analysis of the MLC-STT cell by taking into account the device parametric variations and the ambient temperature during write operations.
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