Design und implementierung eines time-to-digitalwandlers für digitale silicon photomultipliers
Design and implementation of a time-to-digitalconverter for digital silicon photomultipliers
- Tez No: 718091
- Danışmanlar: DR. ALEXANDER MEYER, DR. TİM LAUBER
- Tez Türü: Yüksek Lisans
- Konular: Endüstri Ürünleri Tasarımı, Industrial Design
- Anahtar Kelimeler: Belirtilmemiş.
- Yıl: 2021
- Dil: İngilizce
- Üniversite: Rheinisch-Westfälische Technische Hochschule Aachen
- Enstitü: Yurtdışı Enstitü
- Ana Bilim Dalı: Belirtilmemiş.
- Bilim Dalı: Belirtilmemiş.
- Sayfa Sayısı: 84
Özet
Özet yok.
Özet (Çeviri)
The results of the simulations performed on the TDC to determine its performance parameters are summarized in Table 4.1 for the nominal conditions. Comparison with the TDC specifications, and three similar and recent works in the literature are also provided in Table 4.1. Table 4.1: Summary of the TDC Performance. Parameter Nominal Result Specification [1] [15] [9] Technology 28 nm 28 nm 65 nm 40 nm 65 nm Resolution (LSB) 5 ps 5 ps 15 ps 40 ps 5.1 ps Jitter 2 ps rms < 4 ps rms 6.9 ps rms - 5.5 ps Conversion Time 58 ns < 100 ns 15.5 ns 15.6 ns - Dynamic Range 3.97 ns 4 ns 3 ns 1 µs 4 ns DNL 0.4 LSB < 1 LSB 0.5 LSB 0.1 LSB - INL 0.4 LSB < 1 LSB 0.8 LSB 1 LSB - Av. Power Cons. 130 µW Minimum 160 µW* 171 µW 22 µW* Conversion time is obtained by adding the system reset period of 4 ns to the theoretical value given in (2.18). Dynamic range is less than the target value of 4 ns because the TDC is unable to correctly convert the input time difference values in the last approx. 30 ps of the targeted dynamic range. The delay blocks which are used in the LCU make it possible to detect very small input time difference values. However, when ST OP signal arrives right before ST ART signal, i.e. in the end of the dynamic range, these delay blocks distort the formation of accurate logic states and result in incorrect 0 ps conversion result. If required, a slight increase in the period of ST OP signal could be a simple method to reach the intended value. The results show that, under nominal conditions, the TDC meets all specifications except a very slight reduction in dynamic range. However, when the effects of PVT variations are taken into account, significant deviations from the nominal results are observed. Therefore, a calibration mechanism, which is able to adjust the oscillator frequencies by tuning the control voltages of the delay cells in the GRO, is required in order to keep the performance 51 4 Results of the TDC within specifications for the nonnominal conditions as well. Such a calibration can be realized by using the ST OP signal as a reference to first adjust the slow oscillator period by counting the number of oscillation cycles in a certain time frame, and then adjusting the fast oscillator period similarly by counting the number of oscillations it takes for the two signal edges to catch up with a certain initial time difference. A HDL based circuit can be synthesized to implement the necessary algorithm, while a DAC is needed to obtain the analog control voltages in the end. In Table 4.1, average power consumption values with an '*' sign are calculated by using a different approach to this work. These are calculated by assuming a certain value of events per second. For example, 22 µW value provided in [9] is obtained by assuming a single event in every 100 µs. Running our TDC in the same setting would yield an average power consumption of 5.7 µW, which is almost equal to the idle state consumption. Comparing the obtained results with similar work in the literature given in Table 4.1, this work stands out with its high resolution and low average power consumption during conversion and idle state. In addition to advantages provided by the more advanced technology, this is achieved through the LCU, which is a custom design for the specific requirements of the application. The operation is optimized to run as efficient as possible by preventing unnecessary power consumption, for instance, by running the power hungry oscillators only when it is required and turning them off as soon as the conversion is finished. Finally, it should be noted that the three works ([1], [15], [9]) provided in the table are in the advanced stages of the implementation and the given results are obtained by performing tests on the fabricated TDC.
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