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Model tabanlı adaptif LMS hüzmeleme tasarımı ve FPGAüzerinde gerçeklenmesi

Model-based design and FPGA implementation of adaptive LMS beamforming

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  1. Tez No: 741111
  2. Yazar: EŞREF TEMEL
  3. Danışmanlar: DOÇ. DR. TUFAN COŞKUN KARALAR
  4. Tez Türü: Yüksek Lisans
  5. Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
  6. Anahtar Kelimeler: Belirtilmemiş.
  7. Yıl: 2022
  8. Dil: Türkçe
  9. Üniversite: İstanbul Teknik Üniversitesi
  10. Enstitü: Lisansüstü Eğitim Enstitüsü
  11. Ana Bilim Dalı: Elektronik ve Haberleşme Mühendisliği Ana Bilim Dalı
  12. Bilim Dalı: Elektronik Mühendisliği Bilim Dalı
  13. Sayfa Sayısı: 67

Özet

Günümüzde haberleşme sistemlerinde spektral verimliliğin artması ve dalga boylarının küçülmesiyle birlikte hüzmeleme ihtiyacı kaçınılmaz hale gelmiştir. Ayrıca verimi arttırmak adına anten sayısı ihtiyacı artmıştır. Bu durum kompleks olmayan adaptif hüzmeleme algoritmalarını ve düşük kaynak kullanımlı donanım gerçeklemelerini gerekli kılmıştır. Bu hedefleri sağlamak adına günümüzde birçok çalışma yapılmaktadır. Bu tez çalışmasında düşük kaynak kullanımlı LMS (Least Mean Squares - En küçük Ortalama Kare) adaptif hüzmeleme algoritması FPGA (Field Programmable Gate Array - Alanda Programlanabilir Kapı Dizileri) üzerinde gerçeklenmiştir. Model tasarımı Simulink, RTL tasarımı HDL Coder ve doğrulama işlemi FIL (FPGA-in-the-Loop) yöntemi kullanılarak HDL Verifier araçlarıyla gerçekleştirilmiştir. İlk olarak hüzmeleme sistemi Simulink üzerinde yalnızca HDL Coder aracının blokları kullanılarak tasarlanmıştır. Hüzmeleme sistemi uzamsal filtre ve ağırlık hesaplama birimlerinden meydana gelmektedir. Bu birimlerin iteratif ve geri beslemeli olacak şekilde tasarımı gerçekleştirilirken önemli gereksinimlerden biri olan sentezlenebilir frekansı yüksek tutmak için en üst seviyede boru hattı yöntemi uygulanmıştır. Ayrıca donanım kaynaklarından DSP (Digital Signal Processor - Sayısal İşaret İşleyici) kullanımını azaltmak için mevcut gerçeklemelerdeki çarpma işlemi sayısını azaltan bazı basitleştirme yöntemleri uygulanmıştır. Daha sonra modelin doğruluğunu test etmek için çok yollu kanalla birlikte haberleşme sistemi modellenmiştir. Tasarlanan sistemle birlikte MATLAB üzerinde farklı anten sayıları ve kanal modelleriyle testler gerçekleştirilmiştir. Elde edilen ışıma desenleri sistemin doğruluğunu kanıtlamıştır. Sonraki aşamada FPGA üzerinde gerçeklenecek hüzmeleme sisteminin VHDL kodları HDL Coder yardımıyla üretilmiş ve FPGA için sentezlenmiştir. Bununla birlikte çalışabileceği en yüksek frekans belirlenmiştir. Daha sonrasında hızlıca doğrulama yapabilmek için FIL ortamı tasarlanmıştır. RTL tasarımı gerçekleştirilen birim Zedboard içine gömülmüştür ve referans modelle birlikte simülasyonlar gerçekleştirilmiştir. Elde edilen sonuçlara bakıldığında referans modelle RTL tasarım için birebir aynı çıkışlar elde edilmiştir. Hızlıca model tabanlı tasarlanıp FIL yöntemiyle FPGA üzerinde doğrulaması gerçekleştirilebilen sistemin gerçekleme sonuçları yapılan bazı çalışmalarla kıyaslanmıştır. Bunun sonucunda kaynak kullanımı ve sentezlenebilir frekans bakımından günümüzdeki bazı gerçekleme sonuçlarıyla kıyaslanabilir düzeyde olduğu hatta bazı açılardan daha iyi sonuç elde edildiği görülmüştür.

Özet (Çeviri)

Today, the increase in the number of devices and data usage in communication networks exceeds the capacity of old communication networks such as 4G LTE. New generation communication technologies such as 5G provide a more efficient network infrastructure to meet these challenges and provide high data rate requirements. To meet these requirements, new technologies are introduced and also current technologies are improved in some aspects. One of these technologies is beamforming technology to be used in large antenna array systems. The number of antennas in such systems increases continuously. Like many communication technologies, beamforming algorithms are based on signal processing. Due to the high-speed requirements in signal processing algorithms, it is common for these algorithms to be implemented on FPGA or ASIC with their cost-effective, fast and programmable structure. To achieve these goals, many studies about FPGA and ASIC implementation of beamforming algorithms are carried out today. Beamforming is a process that works with an array of sensors to offer flexible spatial filtering. In the past, spatial filters were designed to produce pencil beams to pick up a signal originating from a single field while eliminating signals from other locations which are undesired signals. Beamforming is a term used for both transmitting and receiving the signal. There are some types of beamforming algorithms in the literature such as data-independent, statistical optimum, and adaptive. However, in this study, adaptive beamforming algorithms were investigated. The beamformer uses an adaptive system that continuously changes the array weights according to an adaptive algorithm to produce an independently controllable beam. With these algorithms, adaptive beamforming weights converge some stationary values. The beamforming algorithm is usually determined based on application requirements such as reliability, resources, and fast convergence. The adaptive beamforming algorithm falls into three categories: blind, semi-blind, and non-blind. In non-blind beamforming, the desired reference signal is required to obtain proper performance. There are several types of non-blind beamforming algorithms such as RLS minimizing the sum of squared errors for a given sample window or MVDR maximizing SINR (Signal to Interference Noise Ratio). The algorithms may differ in terms of convergence time, accuracy or complexity. In this thesis, one of the low complex non-blind beamforming algorithms is focused which is LMS. This algorithm adapts the beamforming weights to make the mean square error signal minimum with a feedback loop. In this thesis, the low-resource LMS adaptive beamforming algorithm was implemented on FPGA with a model-based design approach. Model design and simulations were carried out on Simulink and Phased Array System Toolbox, RTL design was carried out with HDL Coder and was validated by HDL Verifier tools using FIL method. In addition to using HDL languages such as VHDL and Verilog with the traditional method to program FPGAs as the first method, a new model-based design method is emerging by reducing hardware development times with newly developed software such as HDL Coder. HDL Coder is a MATLAB tool which allows to generate VHDL or Verilog code with MATLAB and Simulink blocks. This tool also helps to prototype swiftly with some structural optimization properties such as pipelining or resource sharing. On the other hand, FIL can be used for testing the hardware implementation with the gold reference model in MATLAB or Simulink. The unit to be tested using FIL is programmed for a development board and the testbench is applied from MATLAB or Simulink running on the PC. Initially, the beamforming test environment was designed on Simulink using only the blocks of the HDL Coder toolbox to obtain the best results of synthesis in terms of utilization and frequency. The beamforming system consists of spatial filter and adaptive weight calculation units. The weight calculation unit performs the weight calculation adaptively using the input signal and the desired signal while the spatial filter unit basically removes spatial noise from the system by performing the task of multiplying the conjugate of the beamforming weights with the input signal. These units work in an iterative and feedback manner. While designing the units, the retiming and pipeline methods were applied in order to raise the synthesizable frequency, which is one of the important new generation technologies requirements. Synthesizable frequency is directly proportional to throughput since each sample represents the data symbol. In addition, in order to reduce the use of DSP from hardware resources, a number of methods have been applied to reduce the number of multiplication operations in existing implementations. In the weight calculation unit, the step size was kept constant, and the sign of input signal was used to get rid of some multiplication operations. Then, a high-level system has been modeled to measure the performance of the beamforming unit for which the model design has been carried out and to perform the HDL design. The system consists of a random number generator, modulator, multipath channel, and adaptive beamforming unit. EVM calculator and constellation diagram are also added for performance measurement. Tests were carried out with different antenna numbers and channel models on MATLAB. Simulations were performed until convergence of adaptive beamforming weights. For all antenna configurations, radiation patterns were obtained for a certain angle of arrival by using uniform linear array antennas model on MATLAB. The obtained radiation patterns proved the accuracy of the system. The model is designed parametrically. Before the start of the simulation at the compilation stage, all parameters are determined with an m file. Parameters include modulation level, wave frequency, fixed point lengths, and shift amount that determines step size, sampling time. Some simulations are performed by changing these parameters. In the next stage, VHDL codes were produced with the help of HDL Coder, the beamforming system to be implemented on the FPGA, and synthesized for Xilinx Kintex FPGA. Vivado tool was used from the Simulink screen in the synthesis phase. For this operation, HDL Workflow Advisor property is exploited. The highest frequency at which the system can operate was determined by performing a timing analysis on the synthesis results. The FIL environment was designed in order to be able to verify quickly afterward. The RTL-designed unit was embedded in the Zedboard by following the FIL Wizard flow and simulations were performed with the reference model. It has been observed with the controller designed in the FIL environment that the results obtained at the RTL design output give exact results with the reference model. The implementation results of the system, which can be quickly designed based on a model and verified on the FPGA with the FIL method, are compared with some studies. One of them implements a variaton of the LMS algorithm with the help of HLS which increases performance with parallel structure. The other one implements LMS with the configurable number of antenna and targets low resource usage. As a result, this work is comparable to some current implementation results in terms of resource utilization and synthesizable frequency, and even better in some aspects.

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