Gan güç transistörlerinin anahtar kayıplarının nöral ağ tabanlı modellenmesi

Neural network based modeling of switching losses in gan power transistors

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Tez No: 992577
Yazar: ALİİMZA DAŞDEMİR
Danışmanlar: DOÇ. DR. MEHMET ONUR GÜLBAHÇE
Tez Türü: Yüksek Lisans
Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
Anahtar Kelimeler: Belirtilmemiş.
Yıl: 2026
Dil: Türkçe
Üniversite: İstanbul Teknik Üniversitesi
Enstitü: Lisansüstü Eğitim Enstitüsü
Ana Bilim Dalı: Elektrik Mühendisliği Ana Bilim Dalı
Bilim Dalı: Elektrik Mühendisliği Bilim Dalı
Sayfa Sayısı: Belirtilmemiş.

Özet

Galyum nitrür (GaN) tabanlı geniş bant aralıklı güç transistörleri, yüksek kırılma elektrik alanı, yüksek elektron hareketliliği ve düşük parazitik kapasitansları sayesinde modern güç elektroniği sistemlerinde önemli bir konuma sahiptir. Bu özellikler, GaN tabanlı aygıtların geleneksel silikon tabanlı güç yarıiletkenlerine kıyasla daha yüksek anahtarlama frekanslarında ve güç yoğunluklarında çalışmasına olanak tanımakta; havacılık, otomotiv elektroniği, yenilenebilir enerji sistemleri ve yüksek frekanslı DC DC dönüştürücüler gibi uygulamalarda önemli verim ve hacim avantajları sunmaktadır. Bununla birlikte, GaN transistörlerin çok hızlı anahtarlama davranışı, anahtarlama kayıplarının doğru modellenmesini zorlaştıran karmaşık ve doğrusal olmayan etkileri de beraberinde getirmektedir. GaN güç transistörlerinde anahtarlama kayıpları; gerilime bağlı doğrusal olmayan kapasitanslar, paketleme ve baskı devre kartı kaynaklı parazitik endüktanslar, dinamik kanal direnci etkileri ve geçici anahtarlama anlarında oluşan yüksek frekanslı salınımlar gibi çok sayıda etkileşimin birleşimiyle belirlenmektedir. Bu etkiler nanosaniye mertebesinde gerçekleşmekte ve güçlü bir şekilde birbirine bağlı davranış sergilemektedir. Bu nedenle, geleneksel analitik kayıp modelleri ve üretici veri sayfalarına dayalı yaklaşımlar, gerçek çalışma koşullarında güvenilir anahtarlama kaybı tahmini yapmakta yetersiz kalmaktadır. Bu çalışmada, söz konusu sınırlamaların aşılması amacıyla GaN güç transistörlerinin anahtarlama kayıplarının tahmini için yapay sinir ağlarına dayalı, veri güdümlü bir modelleme yaklaşımı önerilmektedir. Önerilen yöntem, basitleştirici fiziksel varsayımlara veya statik model parametrelerine dayanmak yerine, deneysel olarak elde edilen ölçüm verileri üzerinden çalışma koşulları ile anahtarlama kayıpları arasındaki doğrusal olmayan ilişkiyi doğrudan öğrenmeyi hedeflemektedir. Bu sayede, cihaz fiziği, parazitik etkiler ve sistem seviyesindeki etkileşimler tek bir model çatısı altında bütüncül olarak temsil edilebilmektedir. Önerilen nöral modelin geliştirilmesi için İstanbul Teknik Üniversitesi Güç Elektroniği Laboratuvarı'nda özgün bir deneysel karakterizasyon platformu tasarlanmış ve kurulmuştur. Yüksek frekanslı senkron alçaltan dönüştürücü tabanlı bu platform, anahtarlama kayıplarının kontrollü ve tekrarlanabilir biçimde ölçülmesine olanak sağlamaktadır. Baskı devre kartı yerleşimi, akım döngülerinin minimize edilmesi, düşük parazitik elemanlı bileşen seçimi ve kapı sürme devresinin dikkatli tasarımı gibi donanımsal önlemler sayesinde ölçüm doğruluğu artırılmış ve elde edilen verilerin cihazın gerçek anahtarlama davranışını yansıtması sağlanmıştır. Çalışma kapsamında, biri artırılmış kapılı (enhancement-mode) GaN HEMT, diğeri ise kaskod yapılı GaN FET olmak üzere iki farklı ticari GaN aygıt mimarisi incelenmiştir. Giriş gerilimi, yük akımı ve anahtarlama frekansı gibi temel elektriksel parametreler geniş bir çalışma aralığında taranarak kapsamlı bir deneysel veri kümesi oluşturulmuştur. Anahtarlama kayıpları, giriş ve çıkış güçleri arasındaki fark esas alınarak dolaylı ölçüm yöntemiyle hesaplanmış; bu sayede iletim ve pasif eleman kayıpları analitik olarak ayrıştırılmıştır. Elde edilen deneysel veri kümesi kullanılarak eğitilen yapay sinir ağı modeli, her iki GaN mimarisi için de geniş çalışma koşulları altında yüksek doğrulukla anahtarlama kaybı tahmini yapabilmiştir. Sonuçlar, geleneksel analitik modellere kıyasla özellikle yüksek frekans ve yüksek gerilim bölgelerinde belirgin doğruluk artışı sağlandığını göstermektedir. Bu çalışma, GaN güç transistörlerinin anahtarlama kayıplarının modellenmesinde veri güdümlü nöral yaklaşımların güçlü ve ölçeklenebilir bir alternatif sunduğunu ortaya koymakta; ileri seviye güç elektroniği tasarımlarında güvenilir kayıp tahmini için önemli bir katkı sağlamaktadır.

Özet (Çeviri)

Gallium Nitride (GaN)–based wide-bandgap power transistors have become a cornerstone technology in the evolution of high-performance power electronic systems, primarily due to their outstanding material properties such as high breakdown electric field strength, superior electron mobility, and intrinsically low parasitic capacitances. These characteristics enable GaN devices to operate at substantially higher switching frequencies and power densities compared to conventional silicon based power transistors, resulting in significant improvements in efficiency, volumetric power density, and dynamic performance. Consequently, GaN power devices are increasingly adopted in demanding application domains including aerospace power systems, avionics, electric and hybrid vehicles, renewable energy interfaces, and high-frequency DC–DC and AC–DC converters. Despite these advantages, the accurate modeling of switching losses in GaN power transistors remains a critical challenge. The extremely fast voltage and current transition rates inherent to GaN devices introduce complex and highly nonlinear loss mechanisms that are difficult to capture using conventional analytical approaches. Switching losses in GaN transistors are strongly influenced by voltage-dependent nonlinear capacitances, parasitic inductances associated with device packaging and PCB layout, dynamic channel resistance behavior, and high-frequency ringing phenomena during transient switching events. These effects occur on nanosecond time scales and exhibit strong coupling, rendering traditional physics-based analytical models and static datasheet parameters insufficient for reliable loss prediction under realistic operating conditions. In practical converter design workflows, this modeling inadequacy leads to significant uncertainty during efficiency estimation and thermal design. Designers often compensate for this uncertainty by applying conservative safety margins, which may result in oversized cooling solutions and suboptimal power density, or, conversely, by underestimating losses, which can compromise long-term reliability. Therefore, there is a strong motivation to develop alternative modeling strategies that can accurately represent the complex nonlinear behavior of GaN switching losses without relying on oversimplified assumptions. This work proposes a data-driven modeling framework based on artificial neural networks (ANNs) for high-accuracy estimation of switching losses in GaN power transistors. Unlike conventional analytical models, the proposed approach does not require explicit physical equations or simplified equivalent circuit assumptions. Instead, it directly learns the nonlinear mapping between operating conditions and measured switching losses from experimental data. By doing so, the neural model inherently captures the combined effects of device physics, parasitic elements, and system-level interactions within a unified and compact representation. To support the development of a physically meaningful and robust neural model, a dedicated experimental characterization platform was designed and implemented at the Istanbul Technical University Power Electronics Laboratory. The platform is based on a high-frequency synchronous buck converter topology, selected for its suitability in controlled switching loss characterization and its relevance to practical half-bridge power conversion systems. Considerable attention was devoted to hardware design aspects, including optimized PCB layout, minimized current loop areas, low equivalent-series-inductance passive components, and carefully engineered gate-drive circuitry. These measures were essential to suppress parasitic-induced measurement distortions and to ensure that the acquired data accurately reflect intrinsic device switching behavior. Two commercially available and technologically distinct GaN power transistor architectures were selected as case studies. The first device is an enhancement-mode (E-mode) GaN HEMT featuring an integrated p-GaN gate structure, which enables normally-off operation while maintaining very low gate charge and output capacitance. The second device is a cascode GaN FET architecture, combining a high voltage GaN HEMT with a low-voltage silicon MOSFET to achieve standard gate drive compatibility. These architectures exhibit markedly different dynamic characteristics, making them well suited for evaluating the generality and transferability of the proposed neural modeling methodology. A large-scale experimental dataset was generated by systematically varying key electrical operating parameters, including input voltage, load current, and switching frequency, across a wide operating envelope representative of high-frequency power conversion applications. More than seven hundred distinct operating points were recorded, providing a rich and diverse dataset for supervised learning. Switching losses were extracted using an indirect power measurement technique based on the difference between measured input and output power, allowing conduction and passive component losses to be analytically separated. This method avoids the bandwidth and noise limitations associated with direct high-speed waveform integration, thereby improving measurement robustness and repeatability. The resulting dataset was employed to train a feed-forward artificial neural network configured for regression-based loss estimation. Input features were limited to electrical operating variables, reflecting the intended use of the model as a practical design-oriented tool. Prior to training, the data underwent preprocessing steps including normalization, outlier screening, and consistency checks to enhance numerical stability and generalization capability. Multiple network topologies were evaluated by varying the number of hidden layers, neuron counts, and activation functions, and the final architecture was selected based on predictive accuracy and robustness considerations. The trained neural model demonstrated strong agreement with experimental measurements across the full range of tested operating conditions for both GaN device types. The model successfully captured nonlinear loss trends associated with increasing switching frequency and voltage stress, as well as architecture-dependent dynamic behaviors that are not adequately represented by conventional analytical formulations. Comparative evaluation revealed that datasheet-based and analytical loss models exhibit increasing deviation from experimental results at higher frequencies, whereas the proposed neural model maintains high predictive accuracy even in regimes where parasitic effects dominate. The robustness and generalization capability of the neural model were further validated using statistical error metrics and cross-validation techniques, confirming that the learned relationships extend beyond the training dataset. To enhance practical usability, the neural loss estimator was implemented within a graphical user interface that allows real-time comparison with traditional analytical loss calculations. This implementation demonstrates the potential of the proposed approach as an effective design-support tool for power electronics engineers, enabling rapid and reliable loss estimation during early-stage converter design and optimization. Overall, the results of this study indicate that neural network–based modeling constitutes a powerful and scalable alternative to traditional analytical methods for switching loss estimation in GaN power transistors. By implicitly incorporating parasitic effects and nonlinear interactions without explicit physical modeling, the proposed framework significantly reduces prediction uncertainty and improves design confidence. The methodology is device-architecture agnostic and can be readily extended to other wide-bandgap semiconductor technologies, such as silicon carbide (SiC), as well as to more advanced applications including digital twin development and automated design optimization. In addition to predictive accuracy, an important contribution of the proposed modeling approach lies in its ability to abstract complex physical interactions into a compact and computationally efficient representation. Conventional physics-based switching loss models often require detailed parameter extraction procedures, iterative numerical solvers, or high-fidelity time-domain simulations, all of which significantly increase computational burden during converter design and optimization. In contrast, once trained, the proposed neural network model provides near-instantaneous loss predictions without the need for iterative calculations or circuit-level simulations. This characteristic makes the model particularly well suited for iterative design workflows, parametric sweeps, and optimization algorithms where thousands of loss evaluations may be required within short time frames. Another notable aspect of the proposed methodology is its reduced dependency on proprietary or difficult-to-measure device parameters. Analytical switching loss models typically rely on detailed capacitance–voltage characteristics, internal gate resistance values, and package-specific parasitic inductances, many of which are either incompletely specified in manufacturer datasheets or vary significantly between production batches. By contrast, the neural network model implicitly learns the combined effect of these parameters through experimental data, eliminating the need for explicit parameter identification. This property enhances the practical applicability of the approach, particularly in industrial environments where rapid device evaluation is required and detailed physical modeling data may not be available. The proposed neural modeling framework also provides a valuable tool for comparative analysis between different GaN device architectures. By training and evaluating separate models for enhancement-mode and cascode-based GaN transistors under identical test conditions, the study enables a systematic assessment of architecture-dependent switching loss behavior. Such comparisons are difficult to perform using analytical models due to architecture-specific assumptions and model structures. The data-driven nature of the neural approach allows these differences to emerge naturally from measured behavior, offering designers deeper insight into the practical trade-offs between different GaN technologies. From a system-level perspective, the improved accuracy of switching loss prediction directly translates into more reliable thermal and efficiency assessments at the converter level. Accurate loss estimation enables more precise heat sink sizing, reduced thermal design margins, and improved confidence in long-term reliability projections. This is particularly critical in applications with strict volume, weight, and reliability constraints, such as aerospace and automotive power electronics, where overdesign is costly and underdesign may lead to catastrophic failure. The proposed approach therefore contributes not only to device-level modeling but also to holistic system-level design optimization. It is also important to note that the proposed methodology complements, rather than replaces, traditional physics-based modeling approaches. While analytical models provide valuable insight into fundamental loss mechanisms and scaling trends, neural network–based models excel in capturing complex interactions that arise in practical implementations. The combination of experimental characterization and machine learning thus represents a hybrid paradigm in power electronics modeling, where data driven techniques enhance and extend the applicability of classical engineering methods. The scalability of the proposed framework represents another significant advantage. Although this study focuses on discrete GaN power transistors operating in a synchronous buck topology, the underlying methodology is readily extendable to other converter topologies, operating modes, and semiconductor technologies. By appropriately expanding the experimental dataset and retraining the neural model, the same framework can be adapted to multi-level converters, resonant topologies, or alternative wide-bandgap devices such as silicon carbide MOSFETs. This flexibility highlights the potential of neural modeling as a unifying approach for loss estimation across diverse power electronics applications. Finally, the results of this work highlight a broader methodological shift in power electronics research toward data-driven and learning-based modeling techniques. As switching frequencies continue to increase and device parasitics play an increasingly dominant role in system behavior, purely analytical models are likely to face growing limitations. Neural network–based approaches, when grounded in carefully designed experimental characterization, offer a powerful means of addressing this complexity. The findings presented in this study demonstrate that such approaches can achieve high accuracy, robustness, and practical usability, positioning them as a valuable tool for both academic research and industrial power electronics design.

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