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Variability and reliability in nanoscale circuits: Simulation, design, monitoring, and characterization

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  1. Tez No: 401060
  2. Yazar: MUSTAFA BERKE YELTEN
  3. Danışmanlar: DR. MICHEAL B. STEER, DR. PAUL D. FRANZON
  4. Tez Türü: Doktora
  5. Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
  6. Anahtar Kelimeler: Belirtilmemiş.
  7. Yıl: 2011
  8. Dil: İngilizce
  9. Üniversite: North Carolina State University
  10. Enstitü: Yurtdışı Enstitü
  11. Ana Bilim Dalı: Belirtilmemiş.
  12. Bilim Dalı: Belirtilmemiş.
  13. Sayfa Sayısı: 215

Özet

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Özet (Çeviri)

At the nanoscale, variability of transistor process parameters and time-based reliability degradation (also called device aging) significantly impact circuit performance metrics. It is necessary to individually model the variability of each transistor in a circuit to accurately represent die-to-die and within-die variations. Traditionally, one of several sets of process parameters is used for all transistors in a circuit in what is called process corner analysis. Reduced-order models are developed to rapidly analyze and simulate circuit variability and reliability simultaneously. The main advantage of reduced-order models is integrating multiple parameter sweeps by greatly reducing the dimensionality of a transistor process model to just those parameters subject to significant variability. The surrogate models also include models of aging that are not part of a transistor model. Other effects could also be incorporated. The drain-source currents of 65 nm n- and p- channel transistors are modeled using surrogate models, neural networks, and support vector machines. The models are in terms of eleven parameters, including a few process parameters that essentially cover the process variation space, terminal voltages, temperature and device age. The reducedorder models are compared on the basis of the model generation and evaluation times, model size, and accuracy. Kriging-based surrogate models and neural network-based models are shown to have sufficient accuracy to perform circuit variability and reliability analysis with Kriging-based models having a shorter evaluation time for smaller circuits and neural network-based models having shorter evaluation time for larger circuits. Variability in operating conditions of differential amplifiers is accurately captured using the reduced-order models. The effects of die-to-die and within-die variations on voltage transfer characteristics of an XOR gate are presented. Individual contributions of crucial process parameters to drain current mismatch of two transistors are quantified with the largest contributions coming from intrinsic threshold voltages and effective length variations of devices. Reliability degradation in differential amplifiers in the presence of process variations are investigated. Design for reliability guidelines are formulated suggesting that the biasing of analog circuits should be modulated by changing nodal voltages within a circuit to increase device aging resilience. An analog circuit-based negative bias temperature monitor is designed and implemented in 65 nm device technology yielding a sensitivity of 3.15 V−1. Finally, experimental aging characterization examples have been conducted on major analog and digital building blocks.

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