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Mos tranzistorlarda kanal katkılama yönteminin oksit ve arayüzey tuzakları üzerine etkisi

The Channel doping method's effect on oxide and interface traps in mos transistors

  1. Tez No: 100744
  2. Yazar: ENGİN KONUR
  3. Danışmanlar: PROF.DR. UĞUR ÇİLİNGİROĞLU
  4. Tez Türü: Doktora
  5. Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
  6. Anahtar Kelimeler: Belirtilmemiş.
  7. Yıl: 1999
  8. Dil: Türkçe
  9. Üniversite: İstanbul Teknik Üniversitesi
  10. Enstitü: Fen Bilimleri Enstitüsü
  11. Ana Bilim Dalı: Belirtilmemiş.
  12. Bilim Dalı: Belirtilmemiş.
  13. Sayfa Sayısı: 90

Özet

MOS TRANZİSTORLARDA KANAL KATKILAMA YÖNTEMİNİN OKSİT VE ARAYÜZEY TUZAKLARI ÜZERİNE ETKİSİ ÖZET Bu çalışmada, tümdevre MOS tranzistorların üretim süreçlerinde kullanılan iki farklı kanal katkılama yönteminin, tranzistorların güvenilirliği ve ömrü konusunda önemli rol oynayan oksit ve arayüzey tuzakları üzerine etkisi incelenmiştir. İncelenen iki farklı yöntemden birincisinde tranzistorların kanal bölgesi, bir ön oksit üzerinden Bor iyonu implantasyonu ile katkılanmış sonra geçit oksiti büyütülmüştür, diğer yöntemde ise kanal katkılaması doğrudan geçit oksiti üzerinden Bor iyonu implantasyonu ile yapılmıştır. Bu iki yöntemden hangisinde, yapıdaki tuzaklama mekanizmaları nedeniyle bozulmanın daha az olduğunun ve bu sayede hangi yöntemin daha güvenilir ve daha uzun faydalı ömüre sahip tranzistorlar üretilmesini sağladığının bulunması amaçlanmıştır. Arayüzey ve oksit tuzakları, MOS tranzistorların akım taşıma yeteneklerinde bozulmaya; eşik gerilimi, geçiş iletkenliği, eşikaltı eğimi, doyma bölgesi akımı gibi parametrelerin değişmesine sebep olurlar. Bu bozulma, tranzistorların çalışma süresi uzadıkça artarak devam eder ve faydalı ömür olarak tanımlanan süre sonunda tranzistorların kendilerinden beklenen fonksiyonu yerine getirememelerine sebep olabilir. Arayüzey tuzak yükleri pozitif veya negatif olabilir. Yapısal ve oksitleme prosesine bağlı bozucular veya metal kirlenmesi veya sıcak taşıyıcı gibi Si-Si02 arayüzeyindeki bağ yapısını bozucu etkiler nedeniyle oluşabilirler ve silisyum ile elektriksel iletişimde bulunurlar. Oksit içi tuzak yükleri ise oksit içinde tuzaklanan elektron veya delikler nedeniyle oluşurlar, pozitif veya negatif olabilirler, silisyumla elektriksel iletişimde bulunabilirler. Bir tuzağın bir taşıyıcıyı yakalama kabiliyeti tuzağın yakalama kesiti ile açıklanır. Ortalama serbest yolu, yakalama kesitinin yarıçapından küçük olan taşıyıcı; bozucu tarafından yaratılan potansiyel kuyusuna tuzak yarıçapından daha yakın olursa tuzaklanacaktır. Arayüzey tuzak yoğunluklarının ve arayüzey tuzak yakalama kesitlerinin ölçülmesinde, yük pompası akımı tekniği kullanılmıştır. Bu yöntem, küçük boyutlu tranzistoriarda yüksek duyarlılıkla istenen büyüklükleri ölçmeye imkan vermektedir. Yöntem, kaynak ve savak bölgeleri elektriksel olarak kısa devre edilmiş MOS tranzistorların geçit elektroduna, tranzistoru her bir periyotta, evirtim ve yığılma rejimlerine götüren uygun genlikte ve seviyede periyodik işaret uygulandığında, taban elektrodundan, tuzakların miktarı ve kesitiyle orantılı akan akımı ölçme ilkesine dayanmaktadır. Bu yöntemle 1x109 [cm“2 *eV1] mertebesinde tuzak yoğunluğu ölçümü mümkündür. Çalışmada kullanılan iki farklı yük pompası tekniği, iki farklı kanal katkılama yöntemiyle üretilen NMOS ve PMOS tranzistorlara uygulanmıştır. Birinci yük pompası yönteminde, tranzistorun geçit terminaline; genliği ve ofset gerilimi sabit tutulan ve frekansı değiştirilen üçgen dalga işareti uygulanmıştır. Kaynak ve savak terminalleri birbirine bağlanıp tabana göre tıkama yönünde 0.2V gerilim ile IXkutuplanmıştır. Taban terminal akımı - frekans ilişkisinden arayüzey tuzak yoğunluğu ve yakalama kesitleri bulunmuştur, ikinci yük pompası yönteminde genliği ve frekansı sabit tutulup ofset gerilimi değiştirilen kare dalga işareti geçit terminaline uygulanmış, kaynak ve savak jonksiyonları birinci yöntemdeki gibi kutuplanmıştır. Yük pompası ölçümleri, tranzistoriara belirli süreyle çeşitli genlikte gerilim zorlaması uygulanmadan önce ve sonra tekrarlanarak arayüzey tuzak yüklerinin yanısıra oksit içinde tuzaklanan yükler hakkında bilgi edinilmiştir. Bu çalışmada elde edilen sonuçlar aşağıdaki gibi özetlenebilir.. Her iki süreç tipi için metalizasyon sonrası tavlama yapılmadan önceki arayüzey tuzak yoğunluğu yaklaşık olarak 1.4x1 011 [cm”2 *eV1] iken azot ortamında tavlama sonucu, 3x10 mertebesine düşmüştür. Tavlama süreç adımında azot içine %13 hidrojen ilave edilmesiyle bu miktar yaklaşık 1.2x1010 olmaktadır.. Arayüzey tuzak yakalama kesitleri her iki tip süreç için tavlamasız durumda 2x1 0“14 [cm2] civarındadır. Bu değer, azot ve azot+%13 hidrojen ortamında tavlama sonucunda bir mertebe küçülerek 2x1 0”15 civarına düşmüştür.. NMOS tranzistorlarda oksit içine delik enjeksiyonu sağlayan düşük geçit gerilimi, yüksek savak gerilimi zorlaması uygulandıktan sonra yapılan ölçümler sonucu, ön oksit üzerinden kanal katkılaması yapılan yöntemde oksit içinde delik tuzaklanmasının, geçit oksiti üzerinden kanal katkılamalı duruma göre daha yüksek olduğu görülmüştür. Bu durum, ön oksit kullanıldığı durumda yüzeye bırakılan Bor atomlarından bir kısmının, daha sonraki geçit oksiti büyütme aşamasında oksit içine kaçarak, oksitin delik tuzaklama mekanizmasını hızlandırması olarak açıklanmıştır.. NMOS tranzistorlarda en fazla bozulmaya neden olduğu öngörülen V0S=Vds/2 gerilim zorlaması öncesi ve sonrası yapılan ölçümler ile, ön oksit üzerinden kanal katkılaması yapılan tranzistorlarda, geçit oksiti üzerinden kanal katkılaması yapılan tranzistorlardakinden daha az arayüzey tuzak yoğunluğu bulunmuştur. Bu sonuç, ön oksit üzerinden kanal katkılaması yapılması durumunda, implantasyon sonrası yapılan geçit oksiti büyütme işleminin, tavlama etkisi nedeniyle arayüzey tuzaklarını azaltması ile açıklanabilir.. Düşük geçit gerilimleri ile zorlanan PMOS tranzistorlardan geçit oksiti üzerinden kanal katkılamalı olanlar daha fazla bozulma göstermişlerdir. SUPREM simulasyonlarına göre, arayüzeye yakın bölgelerde Bor konsantrasyonu, geçit oksit üzerinden kanal katkılamalı olanlarda daha yüksektir. Bor konsantrasyonu ile bozulma arasında bir ilişki kurmak mümkün görülebilir. Sonuç olarak, geçit oksit üzerinden kanal katkılaması yapılan tranzistorlarda arayüzey tuzakları; ön oksit üzerinden kanal katkılaması yapılan tranzistorlarda oksit tuzakları daha etkindir. MOS tranzistorlarda oksit ve arayüzey tuzakları nedeniyle bozulmaya bağlı güvenilirlik ve faydalı ömür açısından iki farklı kanal katkılama yönteminden biri diğerine göre üstün değildir.

Özet (Çeviri)

THE CHANNEL DOPING METHOD'S EFFECT ON OXIDE AND INTERFACE TRAPS IN MOS TRANSISTORS SUMMARY Although Si02 is considered as the best insulating material available for microelectronics, it is far from being perfect. The silica network contains imperfections and impurities. These defects can be electrically active if they introduce energy levels in the Si02 band gap. Defects located in the bulk of SİO2 or at Sİ-SİO2 interface of a MOS device, act as trapping centers if they can capture carriers (electrons or holes) or emit them (when already charged). Carrier trapping gives rise to a space charge (either positive or negative) in the oxide, which modifies the pre-existing electric field and the potential distribution. In order to minimize the influence of electrically active defects and thus increase the useful lifetime of the device, (1) these defects must be detected and identified, (2) their physical, chemical and electronic origin must be determined, (3) when they cannot be avoided, their concentration must be reduced to a minimal value through process improvements. Interface or oxide traps leads to degradation of the MOS transistor current drive capability and affect parameters, such as threshold voltage, the linear region transconductance, the subthreshold slope, the saturation region drive current. This degradation build up with the operation duration of the MOS transistor. At the time called lifetime, transistors can not perform their functional operation due to degradation. Gate oxide quality is the most important key factor. Process improvement of this step, preceding and following steps can minimize the effect of these defects. The channel doping namely threshold adjust implantation method affect the oxide quality. In this study, it is aimed to investigate the channel doping method's effect on oxide and interface traps in order to choose more reliable method in CMOS fabrication. Two type of threshold adjust implantation, which are used frequently in standard CMOS processes, has been considered. Firstly, channel implantation, using boron, has been performed directly through gate oxide. (This process will be called as TGO). Secondly, again with boron, implantation has been done through a sacrificial oxide and then this oxide was stripped before gate oxide growth. (This process will be called as TSO). Moreover, post-metalization low temperature annealing conditions has been investigated using pure nitrogen and hydrogen/nitrogen mixture ambient. The transistors used in this study has been manufactured with 3um n-well CMOS technology in Semiconductor Technology Research Laboratory-YİTAL of National Electronics Institute of TÜBİTAK. In order to measure the interface trap density and capture cross section of the trap, charge pumping technique has been used. In this method, the source and XIdrain of the transistor are connected together and held at a certain reverse bias voltage with respect to substrate. When the transistor pulsed into inversion, the surface becomes deeply depleted and, for NMOS transistors, electrons will flow from the source and drain regions into the channel, where some of them will be captured by the interface traps. When the gate pulse is driving the surface back into accumulation, the mobile carriers drifts back to the source and drain under the influence of the reverse bias, but the charges trapped in the interface traps will recombine with the majority carriers from the substrate and gives rise to a net flow of negative charge into substrate. This is so-called charge pumping effect. The charge Qn which will recombine is given by Qtt = AQ * q * Dn * AE. Where, AG is the channel area of the transistor [cm2], q is the electron charge [C], Da is the interface trap density [cm“2 * eV1 ], AE is the energy interval swept in the bandgap [eV]. When applying repetitive pulses to the gate with frequency f, this charge Qa will give rise to a current in the substrate given by ICp = Qk * f. This substrate current is a measure of the mean value of the interface trap density over the energy range swept by the gate pulse. By showing the recombined charge per cycle, Qk as a function of the frequency on a semilogarithmic plot, one obtains a straight line when using triangular pulses. From the extrapolation of this curve to zero charge, the obtained frequency gives a value for the geometrical mean value of the capture cross sections. The slope of the curve allows the determination of the mean value of the interface trap density without the need for any other parameter than the temperature and the channel area. The sensitivity of the technique has been shown to be better than 1x109 [cm”2 * eV1 ]. Interface trapped charge, (Qrt) may be positive or negative. It is due to (1) structural, oxidation-induced defects, (2) metal impurities, or (3) other defects caused by radiation or similar bond breaking processes (e.g., hot carriers). The interface trapped charge is located at the Si-Si02 interface. It is in electrical communication with the underlying silicon and thus be charged or discharged, depending on the surface potential. Most of the interface trapped charge can be neutralized by low-temperature (450 °C) hydrogen annealing. This charge type in the past has been called surface states, fast states, interface states. Oxide trapped charge, (CU) may also be positive or negative due to holes or electrons trapped in the bulk of the oxide. Trapping may result from ionizing radiation, avalanche injection or other similar processes. A defect acts as a recombination center if its energy level, ET can exchange carriers with both conduction and valence band which usually means that ET is located near the mid-gap. A defect acts as a trapping center if it can capture carrier from, and re-emit it into, the nearest energy band, which is usually means that ET is located near the energy band edge. When the trapping centers are highly concentrated, they interact. This leads to a broadening of the discrete levels and to the formation of energy bands, called impurity bands, inside the bandgap. The ability of the trap to capture a carrier is described by the capture cross section. When there is a free carrier as a diffusing particle of mean free path much smaller than the effective capture radius of the trap, capture is probable if the carrier approaches the potential well, created by defect, at a distance less than radius of the trap. In the charge pumping method, the base level of the gate pulse train can be swept while the amplitude, the frequency, rise and fall times of the pulses keep constant. Five operation regions can be distinguished in the behavior of the substrate current as a function of the base level of the gate pulses. For NMOS transistors, (1) when Vbase < VFB while Vtop > VT ; the conventional charge pumping effect occurs. This means that a net amount of charge is transferred (“pumped”) XIIfrom the source and drain to the substrate via the interface traps each time the transistor pulsed from the inversion toward accumulation and back. (2) when Vbase < Vtop < Vfb ; interface traps are permanently filled with holes and consequently no recombination current is measured. (3) when VT < V^se < Vtop ; the channel is permanently in inversion so no holes reach the surface at any time. For both (2) and (3) cases, the measured substrate current consists of only the source and drain leakage currents. (4) when Vbase < VFB < Vtop < VT ; the charge pumping current increases from zero to a saturation level. The electron concentration at the interface during the inversion part of the gate pulse drastically reduces when the top level does not reach VT. Therefore, the edge of the ICp versus Vbase characteristic obtained for this condition is located at (VT -AVA ), where AVA is the amplitude of the gate pulse. (5) when VFB < V^se < VT < Vtop ; the charge pumping current decreases from saturation level to zero. This edge located at Vfb, since the recombination current disappears when the channel can no longer be flooded with holes By degradation of a MOS transistor due to electrical stress, we understand either the occurrence of a substantial increase of interface traps at the gate- insulator/bulk interface, or a buildup of charges in the gate insulator itself during device operation. This charging is either due to the generation of new traps, or to the filling of existing traps. These changes will affect the electrical characteristics of the transistor. Base level sweep method of charge pumping technique enables to distinguish between the formation of interface traps and the buildup of oxide charge. Indeed, the total number of interface traps in the channel is proportional to the amplitude of the recorded substrate current, while the threshold voltage and the flat-band voltage, which are determined by the oxide charges and the charges in the interface traps, can be directly extracted from the edges of the curve. An increase in the level of the charge pumping current is therefore proof of an increase of the interface trap concentration. A shift of the edges toward more negative voltages is indicative for a net positive charge at the interface, while a shift to more positive voltages indicates the presence of a net negative charge. In many real-life operation modes, transistors are not stressed uniformly over the channel, but the degradation will be rather localized in the channel, mostly near the drain. A typical example is the channel hot-carrier degradation that occurs most dramatically when a short-channel transistor is used in saturation mode. The degradation analysis by means of“conventional”transistor characteristics, such as Ids-Vgs curves, cannot be readily used for nonuniform degradation case. The definition of a threshold voltage loses a great deal of its physical meaning for a channel with nonuniform oxide charge and interface trap distribution. The advantage of the charge pumping technique for the study of nonuniformly degraded channels can be explain as follows. When the channel can be thought of as being composed of several parts with different threshold voltages and different concentrations of interface traps, the resultant charge pumping (CP) signal is the sum of the CP signals of the composing parts. In fact, as far as the CP current is concerned, the complete channel behaves like the parallel circuit of the composing parts. This is not the case for characteristics such as the Ids-Vgs curves, which are the resultant of the series circuit of the composing parts of the channel, and therefore not simply the sum of the characteristics of these composing parts. This considerably complicates the analysis of Ids-Vgs curves. Two different kind of charge pumping technique have been used mainly during this study. Both of them have been applied to two different kind of channel implant process. One of the methods has been used for transistors processed with two different kind of low temperature annealing. XIIIIn the first CP method, the frequency of the triangular gate pulses has been changed while keeping its amplitude and offset voltage constant. A reverse voltage of 0.2 Volt was applied to source and drain. Obtained mean capture cross section ed of the interface traps and average interface trap density-Djt values can be summarized as follows: Drt values before annealing have been obtained from lep/f versus frequency curves about 1.4x1011 [cm“2 * eV1 ] for transistors both process TGO and TSO. After annealing in pure nitrogen ambient, these values decreased to a value of 3x1 010 [cm”2 * eV“1 ]. After annealing in a hydrogen/nitrogen mixture ambient, value of 1.2x1010 [cm”2 * eV“1 ] has been calculated, a values before annealing have been obtained about 2x1 0”14 [cm2 ]. After low temperature annealing in both nitrogen and hydrogen/nitrogen ambient, this value decreased a value of about one order of magnitude lower than those obtained before annealing. Briefly, any difference on Drt or o values for between process TGO and TSO have not been observed in this first CP method. In the second CP method, the offset voltage of the square gate pulses has been changed while keeping its amplitude and frequency constant. A reverse voltage of 0.2 Volt was applied to source and drain. Before applying bias voltage stress, any difference on charge pumping current versus offset voltage characteristics have not been observed for between process TGO and TSO. Different voltage stresses have been applied to the NMOS transistors for various duration in order to investigate hot-carrier behavior of the transistors. After low gate voltage stress (VGs=1V, VDs=10V) and (VQS=1V, Vds=9V) for various duration, an increase of the charge pumping current is observed. The edges of the post-stress AICp (post-stress minus pre-stress) curves exhibit a clear shift toward more negative gate voltage values as compared to the edges of the CP curve of the virgin device. This indicates that the net charge in the system after degradation is positive. This can be caused by trapped holes or by donor-type interface traps. In order to get more information concerning the exact nature of the observed distortion of the CP edges, an additional experiment was carried out. After the duration of somewhat long (500s and 2500s) low gate stress, a brief electron injection (VSs=VDs=10V, t=30s) was performed. After electron injection, the transition edges of the AICp curve shift back toward the ones of the virgin device. However, no significant change in interface trap density is detected after this electron injection(i.e. no increase in the magnitude of AICp). Therefore the first negative shift must be due to holes trapped in the oxide, not to the donor-like nature of the created interface traps. After low gate stress, the distortion of CP curves in process TSO were measured larger than those of process TGO. This observation can be explained as follows: In process TSO, the boron atoms escape into gate oxide during high temperature gate oxide growth because of high diffusivity of boron. In process TGO, threshold adjust implantation is performed after gate oxide growth. The remaining process steps is the same for both TGO and TSO. Therefore, in TSO, there is an additional high temperature process after boron implant. We can conclude that there is more boron in oxide in the type of process TSO, thus this excessive boron concentration increase the possibility of hole trapping. For conventional NMOS transistors, the maximum degradation occurs in the medium voltage range (VGs=Vds/2), and is caused by mobility degradation due to interface trap generation. These interface traps are generated by the simultaneous injections of holes and electrons for these conditions but holes are more effective in generating interface traps. Various duration of medium voltage stresses for VGs=Vds/2=5V and Vgs=Vds/2=5.5V were performed. The distortion of CP curves in process TGO were measured larger than those of process TSO. In other words, xivmore interface traps will be created in process TGO than those of in process TSO. This observation can be explained by the anneal of implantation defects during gate oxide growth performed after TSO implantation. Electron injection case (VGs=Vds=10V) for NMOS transistors was investigated. The distortion in CP curves were the least among different stress conditions examined. There were no difference in between process TGO and TSO. PMOS transistors were DC stressed for various duration at VDs = -11V and different gate biases. For low and intermediate gate voltages, electron trapping is the dominant degradation mechanism. In process TGO, degradation was found larger than those of process TSO. As conclusion, oxide trapping in process TSO; interface trapping in process TGO was measured larger than those of each other. Therefore, from the point of view of reliability and useful lifetime depend on degradation due to oxide and interface trapping mechanism; two different channel doping method have not a superiority to each other. xv

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