VHDL ile lojik devre tasarımı ve DSP uygulamaları için çarpma bloklarının modellenmesi
Başlık çevirisi mevcut değil.
- Tez No: 75391
- Danışmanlar: PROF. DR. AHMET DERVİŞOĞLU
- Tez Türü: Yüksek Lisans
- Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
- Anahtar Kelimeler: Belirtilmemiş.
- Yıl: 1998
- Dil: Türkçe
- Üniversite: İstanbul Teknik Üniversitesi
- Enstitü: Fen Bilimleri Enstitüsü
- Ana Bilim Dalı: Elektronik ve Haberleşme Mühendisliği Ana Bilim Dalı
- Bilim Dalı: Elektronik ve Haberleşme Mühendisliği Bilim Dalı
- Sayfa Sayısı: 140
Özet
ÖZET Bu tezde, sayısal işaret işlemede kullanılacak işlemcilerin tasarımında kullanılmak üzere geşiltirilmiş dokuz farklı çarpma yöntemi incelenmiştir. Bu yöntemlerin içinden VLSI tasarımına ve modellemeye uygun altı tanesinin tasarımı yapılmıştır. Çarpma devrelerinin tasarımları, elde edilen modellerin daha sonra kullanılabilmeleri için nxn bitlik yapılmıştır. Çarpma devrelerinin modelleri bir donanım tanımlama dili olan, VHDL kullanılarak yazılmıştır, n sayısı tasarımcı tarafından değiştirilebilir. Böylece aynı model kullanılarak farklı giriş büyüklüklerine sahip devreler elde edilebilir. İkinci bölümde devrelerin modellerinin yazılmasında kullanılan tanımlama dili VHDL ile ilgili kısa bilgi verilmiştir. Üçüncü bölümde, bu çalışmada sıkça kullanılan temel bilgiler verilmiştir. Bu amaçla sayıların gösterilim şekilleri anlatılmıştır. Ayrıca çarpma devrelerinde toplanacak ara çarpım sayısını yarıya düşürmek için kullanılan Booth algoritması anlatılmıştır. Dördüncü bölümde, incelenen çarpma yöntemleri anlatılmıştır. Bu bölümde dokuz farklı çarpma yöntemi yer almaktadır. Yöntemlerden altı tanesinin VHDL modelleri yazılarak, tasarımları yapılmıştır. Beşinci bölümde, tasarlanan devrelerin alan ve gecikme analizleri verilmiştir. Tasarlanan devrelerin karşılaştırılabilmesi amacıyla farklı n değerleri için alan değerlerinin ve en uzun yoldaki kapı sayılarının gösterildiği bir tablo verilmiştir. Bu tablodaki sonuçlar yardımıyla, daha sonra yapılacak tasarımlarda gereken performans gözönünde bulundurularak hangi çarpma devresinin uygun olduğuna karar verilebilir.
Özet (Çeviri)
SUMMARY LOGIC CIRCUIT DESIGN WITH VHDL AND MODELLING OF MULTIPLICATION BLOCKS FOR DSP APPLICATIONS With digital signal processing systems growing in size and complexity, designers require increasingly sophisticated development process. Traditional computer-aided engineering tools, which primarily support the development phase, do not perform effectively in the design of algorithms and architectures. In addition, they often lack facilities for exchange of designs and insertion of new technologies. VHDL addresses these issues and offers the DSP designer a wide range of modeling capabilities for examining algorithms, architecture, and technologies. VHDL (VHSIC or Very High-Speed IC, Hardware Description Language) is IEEE standard language for the description of electronic circuits. It is the language of choice for the majority of ASIC (application-specific IC) designers, and most of the major CAD vendors have integrated VHDL tools into their product lines. These tools include simulators, debuggers, graphics interfaces, and synthesizers. The effective use of VHDL in digital system design depends on the use of existing or off-the-shelf models for portions of the system. These models must not only interact with each other but also multivalue logic system must be compatible with existing and new models. There is a great need for models flexible enough to simulate using many multivalue logic systems. Digital signal processing involves many calculations of the form: A=BC+D (1) This equation involves a multiply operation and an add operation. A machine which can perform the multiply and the add in just one clock cycle, is needed. In real time signal processing, main concern is with the amount of processing can be done before the new item of data arrives which has to be dealt with. Early DSP systems were built using standard components to construct shift-registers, adders, and multipliers. The multiplication operation was rapidly seen as the limiting factor in the performance of these computers. Multiplier design advanced through the use of pipelining techniques and the first single-cycle multipliers were implemented in the early 1970s with standard high-speed emitter-coupled logic (ECL) components. Array multiplier and Wallace tree multiplier are mostly used high speed multiplication methods. Array multipliers are suitable for VLSI design because of their repeated architecture. But the time for multiplication of two n-bit numbers is proportional to n. So for big n, it his method takes long time. In multipliers designed XIwith Wallace tree the time for multiplication is proportional to login. But because of the complex wires in the integrated circuit, they are hard for physical implementation. In this thesis, nine different multiplication methods are examined. Six of the methods are chosen for writing VHDL model. These methods are useful for DSP applications. After writing VHDL models of the multiplication methods, they are synthesized and compared with each other about area and latency. So a designer that will use these multipliers in her/his design can choose one of them easily. All of the designed circuits can be used later in different integrated circuit for DSP. They are designed as they can be used in any application to multiply two numbers that have two to fifty- four bits. The methods used for writing VHDL model of the multiplier are given below. 1. High-Speed VLSI Multiplication Algorithm with a“Redundant Binary Addition Tree [6]. 2. Parallel architecture modified Booth multiplier [7]. 3. A fast multiplier based on the modified Booth algorithm [8]. 4. SPIM: A pipelined 64x64-bit iterative multiplier [9]. 5. A 10-ns 54x54-b Parallel structured full array multiplier [10]. 6. High speed multiplier using redundant binary representation [11]. 7. A new design technique for column compression multipliers [12]. 8. A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach [13]. 9. An 8.8 ns 54x54 bit Multiplier with High Speed Redundant Binary Architecture [14]. In ”High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree“ algorithm a redundant binary representation whose each digit can be 0 or 1 or - 1 is used. It is one of the signed-digit (SD) number representations proposed by Avizienis [15]. A multiplier based on the algorithm is formed by a binary tree of redundant binary adders. This algorithm achieve high-speed computation and a regular structure and can be applied to 2's complement binary integer multiplication. Since a redundant binary number can be itself either positive or negative, it is easy to handle signed numbers. In the algorithm, first the multiplicand and the multiplier are converted into equivalent redundant binary integers and then generate n n-digit partial product represented in the redundant binary representation. These computations can be performed in a constant time independent of n. Next, the partial products are added up pairwise by means of a binary tree of redundant binary adders and obtain the product represented in the redundant binary representation. Since addition of two numbers in the redundant binary number system can be carried out in a constant time independent of the word length of operand, the additions are performed in a time proportional to log2n. Finally, the product is converted into binary representation. The conversion can be performed in a time proportional to log2n by means of an ordinary carry-look-ahead adder (CLA). Thus, n bit multiplication can be performed in a computation time of 0(log2n). The number of xncomputation elements which make up an n bit multiplier based on the algorithm is proportional to n2. Since multiplier is formed by a binary tree of redundant binary adders, it has e regular cellular array structure, and therefore, it is suitable for VLSI implementation. The chip area of it becomes 0(niog2n). ”Parallel architecture modified Booth multiplier“ is a novel implementation of the modified Booth algorithm in which groups of the partial product terms are summed in parallel and these partial results are then combined in a Wallace tree adder array. The final output is formed by an accelerated carry adder. In the conventional modified Booth algorithm (MBA), three-bit segments of the multiplier are scanned and appropriate operation effected on the multiplicand. This scheme generates n/2 rows of partial products where n is the size of the multiplier. ”Fast multiplier based on the modified Booth algorithm“ is an extension of the MBA that involves scanning of four-bit segments in which appropriate operations are effected on the multiplicand to generate n/3 rows of partial products. In this way, the number of adder stages is reduced and speed of the multiplier is increased compared to that of the multiplier using the QMB algorithm. In using this version of the MBA algorithm there is a non-trivial operation, namely, a multiplication of the multiplicand by three. This operation can be accomplished by pre-computing three times the multiplicand by using a carry look-ahead adder that adds the multiplicand with the left-shifted version of the multiplicand. This has resulted in a multiplier that has a lower area x time complexity than the multiplier using the MBA in which three-bit segments are scanned. The structure of ”Parallel structured full array multiplier“ is shown in Fig. 1. This multiplier uses a parallel structure with Booth's algorithm and Wallace 's tree. By applying the Booth algorithm [16], the number of partial products is halved. By n adopting the Wallace tree and a 4-2 compressor, only log2 addition stages are needed in order to add - partial products. This addition is performed in the form of a tournament by using the Wallace tree method. The addition of the partial products used the 4-2 compressor, which can sum up four partial products concurrently. Finally, 2n bit sum and carry is added with the 2n bit carry propagation. In ”High speed multiplier using redundant binary representation“ the two bit Booth algorithm is used for high-speed operation. In the algorithm, a multiplier is recoded into the radix 4 modified signed digit (SD) representation using the digits -2, -1, 0, 1, 2. Then, n/2 partial products can be generated acoording to n/2 recoded multiplier digits. A new method, the ”redundant binary Booth algorithm,“ is used for the partial product generation of the multiplier. In the redundant binary Booth algorithm, n/4 partial products can be generated according to the adjacent recoded multiplier groups. Fig. 1 shows the block diagram of 24-bit x 24-bit multiplier using redundant binary representation. There are four main blocks: the recoder (REC), partial product generator (PPG), redundant binar adder (RBA). xiuMultiplier and Multiplicand A i Booth Algorithm 4:2 Adder X FT Sum and Carry i I Carry Save Adder and CLA Product Fig. 1 Block diagram of the parallel multiplier In the ”Multiplier with High Speed Redundant Binary Architecture“, there are three stages as follows, 1. Partial products (PP) generation and conversion PPs from binary representation to redundant binary representation (RBPP). 2. Addition the RBPPs using Wallace tree with the improved redundant binary adders (RBAs) 3. Conversion RB final product to binary representation N bit numbers A and B by sequences aN-ıaN-2-..ao and bN-ıbN-2-bo respectively. The product of the two numbers can be written as, U=| Ud N-| N-| P = AxB = £ai2ix2>j2j = 2, 2^2 i=() j=0 i=0 j=0 >+J (2) In a straightforward parallel multiplication operation of two N bit numbers, all the N partial products are generated simultaneously and the addition operation between them is carried out by an array of N(N-l) full adders. The multiplication speed is expressed by the delay time associated with the full adders. For the above multiplier, the delay is 2N-1 full adder delays because the longest carry chain that propagates in xivthe array is through the right and bottom edges of the adder array. The algorithm used in this thesis generates a varying (at most N/2) number of partial products, depending on the bit pattern of the multiplier. The algorithm encodes 3-bit strings so the multiplier at a time with an overlapping bit. The multiplier can be written as, yo I Y3 Y3 I y? I yn yn I yis yis i yi9 yi9 i y23 y23 Encoder Encoder Encoder Encoder Encoder * Encoder Encoder Partial Product Generator Partial Product Generator O First Stage Redundant Binary Adder Partial Product Generator nun Partial Product Generator First Stage Redundant Binary Adder 3~~E Second Stage Redundant Binary Adder I Partial Product Generator 1 T Partial Product Generator First Stage Redundant Binary Adder Partial Product Generator 1 I Second Stage Redundant Binary Adder I I Third Stage Redundant Binary Adder T where Fig. 2 Block diagram of 24x24 bit multiplier B= S^b^+b.+b^'^Q^' i=0 (3) Qi=-2b2i+i+bj+b2 i-l (4) XVwith b_]=0 and QjG {-2, -1, 0, +1, +2}. The product of the multiplication can be written as, ?=s AQ^1 (5) i=() An encoder accepts three-bit strings of the multiplier as input and outputs the appropriate control signals. The truth table for the encoder and the mathematical operations effected by each three-bit sequence of the multiplicand is shown in Table 1. The control signals generated by encoder are Z, ADD, 2ADD, 2SUB, SUB and NEC Subtraction can be carried out using 2's complement addition. This involves adding one to the multiplicand at the LSB for SUB and 2SUB operations. The extra one is generated by encoding logic with NEG output. The example below illustrates the principle:, __ 01101 01010 x (2's complements 1001 1) (subtract twice) (subtract once) (add once) result 010000010 Table 1 Truth table for the encoder The subtract twice operation is performed by adding the 2's complement of the multiplicand shifted left by a single bit. The partial product terms are sign extended up to the most significant bit (MSB) of the result. The partial products that are found as mentioned above are converted to RB representation. This is done according to the following consideration. xviThe addition of A and B is expressed as A+B=A-(-B) (6) where A and B are the binary partial products. Using the 2's complement representation, -B can be obtained by complementing all bits of B and then adding a bit ”1“ to the LSB. The procedure expressed as -B=B + 1 (7) where B is obtained by complementing all bits of B. Substitution of (7) into (6) produces the following expression. A+B=A-B-1 (8) If a; and bj are the /th digit of A and B, the following deffnitiorisTare given (aub^ai-b; (9) (A,B) = A-B (10) where b; is the complement of bj. Then the subtraction aj -bj becomes one of the following four forms whose values are 1, 0 or -1: (1,0)=1, (1,1)=(0,0)=0 and (0,1)= -1 (1 1) This means that the pair of (A,B) can be regarded as an RB number having (aj,bj)for each digit. The value of (A,B) is equal to A+B+l from expression (8) and (10). That is A+B=(A,B) - 1=(A,B) + (0,1) (12) because -1 equal to (0,1) from (11). Thus, the RB partial product this equal to the sum of binary partial products, is generated by complementing one of the two partial products and adding (0, 1 ) to the lowest digit. In this RB architecture, an RB partial product can be obtained from two binary partial product only bay complementing one of the pairs because the expression (11) is adopted. No additional hardware is needed. Generated RB partial products are added up by Wallace-tree of redundant binary adders (RBAs). Because an RBA is used for addition of two RB numbers to make one RB number, four inputs are reduced to two output signals. By use of high speed RBA the operating speed can be increased. The addition of the /th digit of two redundant binary numbers (a^,aj”) and (bj\br) expressed by the definition (9) (a:,a:) + (b,+,bi-)^(d:,d,:) (13) where (d*,d^) is the sum. To simplify the consideration, both the inputs (a*,ar) and (bj,b;~) are assumed that take one of the three forms (0,1), (0,0) and (1,0) and no xvn(1,1). By this assumption there are nine kinds of combinations in the sum of (a,+,ar) and (b,+,b|“ ). they are classified into the five cases by the different results of the addition as shown in Table 2. The table shows the intermediate sum (s^, sf ) and carry (c*,cj~) for each case. The carry is added to the sum of the higher digit. The cases 2 and 3 are further divided into two cases by the value of hj from the next lower digit, where h, is defined as follows, (a^a, ) h; = lif ' e (b;,b:) (a^aH h;=0if ' e (bf.bD (0,1) (1,0) (0,1) (0,0) (0,1),(1,0) (0,1) (0,0) (0,1) (0,1) J f(0,0) (1,0) (0,0) (1,0)1 1(0,0) (0,0) (1,0) (1,0) J' (14) The hi is introduced to prevent the continuous carry propagation by eliminating the collision of the sum and the carry from the lower digit. The final sum (d^,d|”) can be expressed as follows: d- =(s- +
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