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3um N-kuyu CMOS teknolojisi ile test kırmığı tasarımı ve tranzistor eşik gerilimi ayarı

Test chip design for 3 um N-well CMOS fabrication technology and threshold voltage adjustment

  1. Tez No: 19260
  2. Yazar: ZEYNEP D. TOROS
  3. Danışmanlar: PROF.DR. DURAN LEBLEBİCİ
  4. Tez Türü: Yüksek Lisans
  5. Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
  6. Anahtar Kelimeler: Belirtilmemiş.
  7. Yıl: 1991
  8. Dil: Türkçe
  9. Üniversite: İstanbul Teknik Üniversitesi
  10. Enstitü: Fen Bilimleri Enstitüsü
  11. Ana Bilim Dalı: Belirtilmemiş.
  12. Bilim Dalı: Belirtilmemiş.
  13. Sayfa Sayısı: 154

Özet

ozan* TÜBiTAK Yarıiletken Teknolojileri Araştırma La boratuarı 'nda çalışmaları sürdürülen 3/-im pol i silisyum geçitli n-kuyu CMOS devre üretiminin ilk aşaması olarak bir test kırnağı tasarlanmıştır. Çeşitli test yapıları nı içeren bu test kırmığının gerçeklenmesindeki amaç, eleman, devre ve proses parametrelerinin elde edilmesi, 1 ayout çizim k ur al 1 ar ı nı n k ont r ol edi 1 mesi, ve güveni lirlik ve rasgele hatanın analizi olarak sayılabilir. Tasarlanan test kırnağının boyutları 3mm x 3mm'dir. Kır mık 2'ye N prob dizisi ile test edilmek üzere, 37 tane farklı modüler test yapısından oluşmaktadır. 2' ye N yaklaşımının özelliği olan modüler yapı nedeni ile, bağ lantı papuçları kırmık Üzerinde önemli bir alan kaplar. Ancak bu şekilde her test yapısı elektriksel olarak bir diğerinden tamamen izole edilmiştir. Ayrıca manuel ölçme işlemi de bu yaklaşım sonucu önemli ölçüde hızlandırıl mış ol ur. Bu tez çalışmasında, TÜBİTAK YİTAL'de ilk defa gerçekleştirilen polisilisyum geçitli n-kuyu CMOS proses adımları ve reçetesi bulunmaktadır. Ayrıca kimi proses adımlarında yararlanılan SUPREM simulasyonları da veril miştir. Çizim kuralları, gerçekleştirilmesi amaçlanan 3jum minimum geometri gözönüne alınarak, laboratuarın o lanakları çerçevesi nce belirlenmiştir. Kırmık tasarımı, layout çizim programı L-EDIT ile yapılmıştır. Her kat mana ait yerleşim planı bu çalışmada yer almaktadır. üretim amaçlı kırmıklardan farklı olarak test kırmığının gerçeklenmesi, tasarlanan test yapılarından elde edilecek verilere dayanarak, prosesin her adımının incelenmesini ve bu şekilde aksayan veya iyileştirilme si gerekli olan yönlerinin ayrıntılı olarak ortaya çı karılmasını mümkün kılar. Bu amaçla tasarımı tamamla nan test yapılarının özellikleri ve çeşitli eleman, dev re veya proses parametrelerinin ölçme yöntemleri her test yapısına ait yerleşim planı ile birlikte anlatıl mıştır. Ölçme yöntemlerine ek olarak, CMOS devrelerde PMOS ve NMOS tranzi s torların eşik gerilimi ayarı da te zin kapsamı içindedir. Uygun eşik gerilimleri elde et mek amacı ile ekilmesi gereken iyon katkı doz ve yoğun lukları hesap yolu ile bulunmuştur. Prosesin tamamlan ması ile, hesap sonucu elde edilen değerlerin ölç üm so nuçları ile karşılaştırılması yapılacaktır. Cv)

Özet (Çeviri)

SUMMARY TEST CHIP DESIGN FOR 3^m N-WELL CMOS FABRICATION TECHNOLOGY AND THRESHOLD VOLTAGE ADJUSTMENT The fabrication of integrated circuits requires a number of processing steps. If one or more of these steps is incorrect or exceeds certain design limits, the circuits will either fail or will not perform as inten ded. The test structures are designed to provide a ra pid analysis technique of a specific portion of the wa fer fabrication process. The microelectronic test chip is composed of various test structures which are measu red by a variety of means to obtain information that is difficult, if not possible, to obtain from product cir cuits. Traditional failure analysis techniques, when applied to a product circuit, are time consuming and hence expensive task. The use of test chips is expec ted to enhance the reliability of the final product and reduce its cost. Test chips have been used by the integrated cir cuit industry since its beginnings in the early 1960s. In general, test chips have been used for component cha racterization, manufacturing process control, equipment and operator performance evaluation, and new wafer fab rication process evaluation. In the early days, test chips were rarely used in the purchase or rejection of circuits or manufacturing equipment. An early test chip was described in the 1968 work of Barone and Myers [1]. They developed a test chip C 1.3mm x 3.0mm > with 44 probe pads to aid in the evaluation of a bipolar 8-bit adder circuit that contained 448 components. In the sa me period, two other test chips are noteworthy. In 1969 Schnable and Keen C2] described a test chip for monito ring LSI reliability life aging. Their chip was desig ned to measure first-level to second-level metal contact resistance, dielectric pinhole density and breakdown, metal step coverage, metal sheet resistance and resis tance of an array of diffused resistors. In 1972, Penney and Lau [3] described a test chip for aluminum-gate PMOS integrated circuits having about 6000 transistors. The test chip ( 0.9mm x 1.3mm > had 200 probe pads and was designed as a reliability evaluation device. It con tains seven electrically testable structures like MOS Cvi)capacitor, MOS transistor, p-n junction diode and in verter for manual probing. The first test chip used to accept or reject wa fers was described in 1974 by Reynolds [4]. Their chip C 2.54mm x 2.54mm > contained 35 test structures and 35 probe pads. It was intended to validate the layout ru les, wafer fabrication process and reliability of alu minum-gate PMOS integrated circuits. The purpose of the test chip was not to control fabrication practices but to assure that the process was under control. Early test chips had limited usefulness; they were not comprehensive and were not designed for automa tic wafer probing. In more recent test patterns, lay outs may be found with small probe pads located within the pattern. Pads are intended for emergency manual probing of certain test structures. In order to meet the automated testability, it was decided that the structures should be designed so that they could be accessed with a 2 by N probe array [5]. The parameter N is an arbitrary positive integer and is limited by the capacity of the test system. The modular arrangement of test structures is a key feature of the 2 by N approach. One disadvantage of this approach is that the probe pads tend to consume a large portion of the available area, making it desirable for the test structures to use as few pads as possible. The test patterns in this ap proach are probe-pad intensive so that they are electri cally isolated from each other. Large test structures are necessary to properly emulate today's complex cir cuits. NBS-28 and NBS-28A designed by Mitchell and Lin- holm C National Bureau of Standards ) [6], have been ar ranged to allow automatic data acquisition. The NBS-28A is a comprehensive test chip C 5.1mm x 5.1mm > for ana lyzing either an NMOS or PMOS self-aligned, junction- isolated process containing 40 test structures and 216 probe pads. To date, microelectronic test chips are manufac tured along with product circuits on wafers. The chips are now being used more frequently in the acceptance or rejection of wafer lots of custom- integrated circuits produced by“silicon foundries”that specialize in the manufacture of custom circuits [7-8]. With the increa sing number of circuits found on a wafer it is no longer possible to accept or reject wafer lots based on circuit performance. Instead, lot acceptance is based on re sults obtained from test chips. Cvii)The test chip designed for TU-MICROFAB project is one of the most important steps, since polysilicon- gate CMOS circuit fabrication will take place for the first time at YITAL-TUBITAK. ITU group of the NATO TU- MICROFAB project focused its interest in developing a design procedure for 3A ions are implanted into the field regions outside theign-W|ll. Implant dose : 10 cm“, Implant energy: 60keV 8. After stripping the photoresist layer a thick SİO2 layer is grown only where SiaN* layer does not exist. This oxide layer is called local oxide or LOCOS. Local oxide thickness: 8680Â 9. Si3N* and pad oxide are etched off and a sacrificial oxide layer is grown to clean the surface from oxi- nitrides which is an undesired material on the gate area. 10. Boron implantation is performed to adjust threshold voltages of NMOS and PMOS transistors simultane ously. The main goal is to achieve +0.8V and -0.8V threshold voltage values. Implant dose: 6x10 cm, 8x10 cm Implant energy: 40keV 11. After removing the sacrificial oxide layer, gate oxide is grown. Gate oxide thickness: 425Â 12. Polysilicon is then deposited with LPCVD method and doped by phosphorus using spin-on technique. Polysilicon gate resistivity: 25û/o 13. Polysilicon layer is patterned by the poly-gate mask forming silicon gates of NMOS and PMOS transistors and interconnections. 14. All regions except p -diffusion regions such as source/drain of PMOS transistos and contact areas to p-substrate are selectively covered by photoresist Ç fifth mask ). Boroç5 implantation is performed. Implant dose: 2.5x10 cm”, Implant energy: 25keV 15. An other photoresist layer is patterned with n source/drain mask which is the negative of p sour ce/drain mask. Arsenic C As ) is implanted. Implant dose: 6x10 cm, Implant energy: 150keV Cix)16. Photoresist layer is removed. A CVD SİO2 is deposi ted and thermal treatment in Nz atmosphere is per formed for annealing of implanted layers and the densification of CVD SİO2. SİO2 layer is deposited to obtain a dielectric la yer between polysilicon and metal. Dielectric layer thickness: 5500Â 17. Contact windows are opened by contact mask. 18. Aluminum, containing %1 silicon is deposited by sputtering technique and patterned with the metal mask. Aluminum thickness: l/4n 19. Finally, a passivation layer of (SİO2) silicaglass is deposited and formed with the passivation mask. To find out the exact process parameters such as ion implantation doses, energies, drive-in and oxidation times, each step of the process has been studied experimentally in laboratory. Basic 3wn n-well polysi licon gate CMOS technology experienced before in litera ture and SUPREM II simulations gave a starting point for experimental work. In accordance to available labora tory equipment and conditions some important modifica tions have been considered in order to determine the exact process parameter values. The first chip designed to be fabricated at YITAL-TUBITAK is a test chip for pa rameter characterization and new wafer fabrication pro cess evaluation. The masks Ml, M2, M4, M5, M7, M8 and M9 were de signed separatly. The design tool is a computer soft ware for PCs called L-EDIT, which gives the possibility to draw every single layer with a different colour. The output file of L-EDIT is in GDS II format [21]. The ge neration of M3 and M6 have been done by the wafer fab rication. M3 is the inverse of n-well mask (Ml), as M6 is the inverse of p+ source/drain mask (M5). A n-well layer and a passivation layer have to be placed beneath all bonding pads with an overlap of 2wn; i.e. n-well overlap of bonding pad is 2/Jm, as metal overlap of pas sivation layer is 2jum. These test structures were designed for a va riety of purposes in the fabrication, in general the six categories of their use are to extract device, circuit and wafer fabrication parameters, check layout rules, and Cx)analyze reliability and random faults. They are de signed in modular arrangement using 2 by N probe array approach. The geometry of square pad used in this lay out is 75/fln x 75/4n with 75/Jm spacing between pads. Pad- to-pad peripheral probe pad access has been also provi ded for circuit blocks using 10 Own x 100/Jm pads. The si ze of the designed test chip is 3mm x 3mm and it is com posed of 37 test structures and 246 probe pads [22-45]. Cell Name Size C/Jm] 1. NHOS and PMOS transistor with minimum 300 x 450 geometry : Wp = 3/Jm Lp = 3/Jm Wn = 3wq Ln = 3fJm 2. Inverter with minimum transistor gate 300 x 300 geometries : Wp = 3/im Lp = 3/Jm Wn = 3/Jm Ln = 3wn 3. Four PMOS transistors with L = 10/Jm and 300 x 450 Wl = 3nm, »2 = 5/Jm, W3 = 10pm, W4 = 20/Jm 4. Four NM0S transistors with L = 10/Jm and 300 x 450 Wl = 3/um, W2 = 5/Jm, W3 = 10/Jm, W4 = 20/Jm 5. Four PMOS transistors with W = 10/Jm and 300 x 450 LI = 3pm, L2 = 5wn, L3 = 10/Jm, L4 = 20/Jm 6. Four PMOS transistors with W = 10/Jm and 300 x 450 LI = 3/Jm, L2 = 5/Jm, L3 = lOffln, L4 = 20/Jm 7. Inverter for inverter threshold 300 x 300 measuring : Wp = 10/Jm Lp = 5/Jm Wn = 5 /ün Ln = 5/Jm 8. PMOS addressable transistor array; matrix 600 x 600 structure consisting of 100 transistors with W = 1/Jtn.... 10/Jm and L = 1/Jm.... 10/Jm 9. NM0S addressable transistor array; matrix 600 x 600 structure consisting of 100 transistors with W = 1/Jm.... lOjum and L = 1/Jm.... 10wn 10. Field-oxide surface leakage structure; 300 x 450 aluminum gate power M0S transistor, comb structure Cxi)11. Gate-oxide surface leakage structure; poly-gate power MOS transistor, serpentine structure 12. Integrated oscillator for latch-up characterization : n-well to n+ active spacing = 10/um 13. Integrated oscillator for latch-up characterization : n-well to n+ active spacing = 7jum 14. Integrated oscillator for latch-up characterization : Using guard rings and n-well to n+ active spacing = 13fm 15. Kelvin resistor structure for contact resistance : p source/drain - metal 16. Kelvin resistor structure for contact resistance : n source/drain - metal 17. Kelvin resistor structure for contact resistance : polysilicon - metal 18. Cross-bridge sheet resistor for PMOS poly-gate sheet resistance and linewidth measurement; linewidth = 16A«n 19. Cross-bridge sheet resistor for NMOS poly-gate sheet resistance and linewidth measurement; linewidth = 16jum 20. Cross-bridge sheet resistor for p sour ce/drain sheet resistance and linewidth measurement; linewidth = 16Mm 21. Cross-bridge sheet resistor for n sour ce/drain sheet resistance and linewidth measurement; linewidth = 16/^m 22. Cross-bridge sheet resistor for n-well sheet resistance and linewidth measure ment; linewidth = ISfJm 23. Breakdown device for n* source/drain - p-substrate junction Size [ma] 300 x 450 300 x 300 300 x 300 300 x 300 300 x 300 300 x 300 300 x 300 300 x 750 300 x 750 300 x 750 300 x 750 300 x 750 150 x 300 Cxii)24. Breakdown device for p source/drain - n-well junction 25. Breakdown device for p-substrate/n-well junction 26. Random fault step-coverage structure; serpentine of metal lines stepping over polysilicon lines 27. Random fault step-coverage structure; serpentine of polysilicon lines stepping over local oxide lines 28. n source/drain - metal contact array; Contact size : 3jum x 3/Jm Contact number = 330 29. p source/drain - metal contact array; Contact size : 3/um x 3fjm. Contact number =330 30. Polysilicon - metal contact array; Contact size : 3pm x 3/Jm Contact number = 520 31. Transmission Gate 32. NAND and HOR Gates 33. Schmitt Trigger 34. Ring oscillator consisting of 11 inverter stages and including a NAND gate trigger Inverter : Wp = 10fm Lp = 5A*m Wn = 5jJm Ln = 5jum 35. Linearized MO S resistive device 36. Resolution structure for each photomask Linewidth = lim IOam 37. Etch control structure for each photomask Linewidth = 1/um 10£fln 38. Chip identification number Size [/urn] 150 x 300 150 x 300 450 x 450 450 x 450 450 x 450 450 x 450 450 x 450 600 x 300 600 x 300 300 x 300 600 x 300 450 x 300 100 x 100 450 x 900 100 x 450 Cxiii)Size [Afln] 39. L-type align marker 100 x 100 40. Stepper align marker 200 x 200 In many MOS IC applications, it is critical to be able to establish and maintain a uniform and stable value of threshold voltage CVt). The value of Vt should not vary with time or with device-operating conditions. An example of the importance of being able to control this parameter involves semiconductor memory devices. Ion implantation technique for adjusting Vt in volves implantation of boron, phosphorus, or arsenic ions into the regions under the oxide of a MOS transis tor. The implantation of boron causes a positive shift in the value of Vt, while phosphorus or arsenic implan tation causes a negative shift. For 3/Jm CMOS process at YITAL -TÜBİTAK, boron implantation is performed to ad just Vt values of NM0S and PM0S transistors. The main goal in this process is to achieve +0.8V and -0.8V threshold voltages. The threshold voltage change OVt) is estimated from, q Nx AVt = c ox where Ni is the dose of implanted ions introduced into the silicon near its surface. The implant is done through the sacrificial oxide layer. Selecting the cor rect implant energy for the sacrificial oxide thickness being used, the peak of the implant occurs at the oxide- silicon interface. After the implant-activating anneal, the implanted distribution is broader than the as - im planted profile. But this calculation gives good esti mates of AVt and therefore, it is often accepted in practice [46-49]. Cxiv)

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