IEEE 1149.1 standardı kullanarak test edilebilir lojik devre tasarımı

Testable lojik circit design by using IEEE 1149.1 standard

Tez No: 22079
Yazar: A.BETÜL TUNCER
Danışmanlar: PROF. DR. AHMET DERVİŞOĞLU
Tez Türü: Yüksek Lisans
Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
Anahtar Kelimeler: Belirtilmemiş.
Yıl: 1992
Dil: Türkçe
Üniversite: İstanbul Teknik Üniversitesi
Enstitü: Fen Bilimleri Enstitüsü
Ana Bilim Dalı: Belirtilmemiş.
Bilim Dalı: Belirtilmemiş.
Sayfa Sayısı: 184

Özet

GZET Elektronik sanayii ve teknolojisinin nazlı gelişmesi beraberinde güvenilirlik problemini getirmekte ve bunun sonucu olarak da test edilebilirlik kavramı önem kazan maktadır. Test edilebilirlik» bir kırmık» kart veya sis temin en kısa surede ve düşük maliyetle» devre Üzerin deki en fazla hatayı yakalama yeteneğidir. Testedilebilirlik tasarı mcılar ve test muhendislri için başlı başına bir problemdir. Bu problemi çözmek için her gün yeni çalışmalar yapılmaktadır. Bu tez çalışmasında» bu probleme cüzüm olarak JTAG* m (The Joint Test Action Group!) ortaya koyduğu ve daha sonra IEEE ta rafından standart kabul edilen yöntem tanıtılmaktadır. IEEE 1149.1 standardı olarak kabul edilen bu yöntem de» giriş vektörleri devreye seri olarak uygulanmakta ve sınır tarama adı verilen yöntemle tüm giriş ve çıkışlar kontrol edilmektedir. JTAG grubu» yukarıda bahsedilen lo- jigin oluşturulabilmesi için» 4 hatlı standart denetim yolunu ortaya koymaktadır. JTAG grubunun bir Üyesi olan Texas Instruments, IEEE 1143.1 standardına uygun olarak SCOPE Ur Un ailesini ve bu standart kullanılarak tasarlanmış kartların testi için donanım ve yazılım içeren ASSET paketini oluşturmuştur. Bu sayede, IEEE 1149.1 standardı kullanılarak kırmık, kart ve sistemlerin üretimine geçilerek, devreye tasarım esnasında test edilebilirlik özelliği kazandırma yolunda, büyük bir ilerleme kaydedilmiştir. Test edilebilirlik konusundaki diğer bir problem de, devrenin test edilebilmesi için gerekli olan giriş test vektör kümesinin oluşturulmasıdır. Tezde bu konuya da değinilmekte ve bugüne kadar geliştirilmiş en geçerli yöntem olan pseudo-random pater n oluşturma yöntemi ninde kullanılan LFSR devresine SCOPE yapısının uygulanması anlatılmaktadır. Bu yöntemde SCOPE yapısının kullanılma sı, yöntemin geliştirilmesi acısından fazla bir fayda sağlamamaktadır. Ancak, yöntem kullanıldığında vektörle rin saklanması için harcanan bellek alanında büyük azalma olduğundan, SCOPE yapısında bu devrenin kullanılması, donanımı basitleştirmekte ve sistemin testinde zaman kazanılmasını sağlamaktadır.

Özet (Çeviri)

SUMMARY TESTABLE LOJIK CIRCIT DESIGN BY USING IEEE 1149.1 STANDARD Nowadays electronic equipments are used both for business and leisure purposes. Nobody takes care about the effort that was spent during the production of these equipments. Besides in the classic development and manufacturing phases C design» development» prototype» etc!) there are steps which are not immediately necessary for production. The functional test or the testability of electronic units are such steps. Their significance is constantly increasing. Test engineers as well as circuit designers are faced with growing problems to test electronic systems» because in the recent years the integration density of ICs» the use of modern chip packages CSMD» PLCO and board layouts C multilayer} are speeded on. Much greater effort is being called to ensure the necessary testing quality. The necessary time for generating test pater ns and for the test operation Itself will increase significantly. Economic testing is scarcely possible because of the small mechanical dimensions that are involved and the resulting cost of adapting an in-eircuit tester. Furthermore, the risk of a faulty test result through imprecise or even incorrect contacting becomes greater. Electronic digital design has been characterized by rapidly increasing performance and functional density at redused cost. End-users have realized these benefits in the form of smaller, more reliable» more capable products with sharp cost drop over time. Continued advances in digital technology will require further miniaturization of geometries that may yield diminishing returns as outpacing the capabilities of debug and test equipment. Present day's board designs are incorporating surface-mount technology to increase the equivalent functionality per unit area. Manufacturers are moving toward slim-profile packages and attempting to reduce the space between parts to pack more“power per picoacre.”Pin-to-pin spacing on catalog devices are approaching 2S mils» with much smaller spacing on many custom and high- pincount ICs. Tape-automated bonding will reduce geometries further» permitting incredibly dense circuit cards to exist more and more use of complex submicron Application-Specific Integrated Circuits C ASICs} and custom devices are occur i ng. ixWhile these trends help to produce smaller and better products» they work directly against the objectives of validating the design and product itself. As ASICs absorb the u functionality of multiple devices» entire sets of bus and control signals are disappeared into the internals of ICs. The complexity associated with validating the design functionality of an IC or board increases exponentially. The geometries of boards defy the state of the art in fixturing technology» including the use of hand-held and clip-on probes. The result has been major concern over continued use of existing approaches to observe and control digital designs. Anticipated benefits in cost and performance are endangered by escalating test costs and product development cycles. Testability ean impact related design support disciplines such as reliability, maintainability» or producibility. The addition of circuits which have testability feature can reduce test costs and time, improving the ease and accuracy of fault detection and isolation. Testability can improve maintainability calculations for mean time to repair by decreasing the test isolation time, but can impact the reliability calculation for mean time between failure negatively by increasing the failure rate. Digital systems, even when designed with highly reliable components, do not operate forever without developing some faults. When a system ultimately developes a fault, it has to be detected and located so that its effect can be removed. Fault detection means the discovery of something wrong in a digital system. Fault location means the identification of the faults with components, functional modules or subsystems, depending on the requirements. Fault diagnosis includes both fault detection and fault location. Fault detection in a logic circuit is carried out by applying a sequence of test inputs and observing the resulting outputs. Although there is no appreciable increase in hardware cost with this metod, the derivation of a complete test set increases the system cost. Also, talcing the system out of service for testing increases the operating cost. If fault diagnosis is executed frequently, then we can expect higher reliability of the system at the cost of maintenance. Conversely if we reduce the frequency of fault diagnosis, then we should pay a penalty for poor reliability of the system while the maintenance cost is reduced.In order to solve this problem without applying periodic fault diagnosis» totally self -checking circuits are used. Circuits with self-testing ability are used in reliable digital systems since they provide a means for immediate detection of certain errors. However, there are also problems associated with the design of such circuits. The basic one of these problems is to design self-checking circuits with adequate checking coverage, that is, designing circuits whose error detection capabilities exceed in some sense their error generating capabilities for those failures that are most likely. Totally self -checking circuits are designed such that they will indicate any malfunction from a prescribed set during normal operation and never produce an erroneous output without such an error indication output. It will be seen that such designs are possible if the prescribed set of malfunctions are restricted to reasonable set of those most likely to occur in a digital eircuit when the components and structure of the circuits are taken into account. To counter any further escalation of test problems it is undoubtedly necessary to come up with and introduce new test tecniques. The concept of hierarchical testability can be seen here as a solution to the diverse problems throughout the product cycle. The hierarchical test is styled to ensure the testability of components and systems, because of their complexity, are extremely difficult to test by conventional methods or maybe can not even be tested at all. The method that is applied, for observing and checking the scan paths, guarantees successful trouble-shooting in complex systems. Special hardware test structures are provided for the purpose, implemented as special -pur pose ICs, standard cells or catalog parts. Besides the graphics processor, the digital signal processor, VLSI devices and ASIC test cells from IEEE 1149.1 standard, these products also include standard bus driver functions C octal buffer, transceiver, register and latent. Their use illustrates how extra possibilities of testing and observation are being offered, especially in critical regions of a circuit. Built-in self -test is the capability for a unit to test itself. The objective is to minimize or eliminate the need for sophisticated external test equipment or manual procedures. When a device has this capability, unlimited access to internal nodes and ability to run at circuit speed is possible. xiAd hoc design for testability techniques are based on guidelines or heuristics» rather than on a systematic or algorithmic methodology. Algorithmic methodology is based on a method of computation that consists of a number of steps performed in a preassigned order» which are specifically adapted to the solution of a problem of a particular type. In ad hoc approach» enourmous gains in testability can be achieved by; proper partitioning» layout and packaging» providing a means of initializing all circuits and placing points of tester access in troublesome areas. The ad hoc testability improvement principles can be used at all assembly levels Cchip» board» and system). The ad hoc design for testability techniques improve testability with a relatively low overhead. This method uses the techniques which are proven and have a known payback. It often makes use of existing resources and it is applicable to off-the-shelf or custom' chip based designs. In this method» rules checking can be automated to some degree. It addresses many aspects of design and packaging. On the other hand» this method does not cover all testability problems. The techniques that ad hoc approach use, are heuristic» but not algorithmic based techniques and also not a structed methodology. The consistency of application not easily ascertained and some rules conflict with others. The structured approach uses a standardized, systematic method of designing sequential circuits such that the need for testing sequential logic in the sequential form is reduced or eliminated, and timing problems associated with race and hazard conditions are eliminated. The method improves accessibility for all testing phases from engineering to production to the field. The techniques establish design for testability CDFT) design rules that can be implemented or validated by computer aided engineering CCAE) tools. Today Structured DFT is considered synonymous with scan path techniques; Williams, and Angel Cor Stanford) scan path, scan set, random access scan, level sensitive scan design Cor LSSCO and boundary Cor external ) scan. Because of the emerging crisis, test engineers in Europe mobilized in 1985 to form the European Test Action Group CETAG3. Iniliated by Philips, this ad hoc organization began promoting a test technique for manufacturing test called“boundary scan.”Boundary scan at temps to overcome the loss of physical access C especially for“ bed -of -nails”fixtures) by embedding virtual test points ar round the periphery of a chip» hence, the name boundary scan. xiiETAG began to approach the major silicon suppliers with their proposal» soliciting support in addressing the emerging test problem. As more non-European companies put its weight behind the proposal» ETAG changed their name to the Joint Test Action Group CJTAGl). Major involvement from leading semiconductor manufacturers, such as Texas Instruments and Motorola» established JTAG as a credible force in advancing test technology. Simultaneously» an IEEE-sponsored effort to establish standard test buses known as IEEE Pi 143.1 emerged in the United States. The currently valid specification is contained in standard IEEE 1149.1 and meets the requirement for testing complex systems in every respect. This standard is partitioned so that both test generation and test analysis» starting at the component level and going through to the testing of complete systems, runs under economic aspects. Access to the test hardware is built by way of a standardized test bus. This is a four wire, serial interface by way of which the test bus can be traced through the circuit like a red threat. The components with the test structure perform the functional test of the particular unit. Depending on the placement of these circuits and how. they are interconnected, there are very different testing possibilities depending on the mode which is selected. These range from the cheeking of connections and terminals through the inspection of whole functional areas Ceg memory, state machine, glue logic!) to the activation of self test functions of the circuits as well as of the test bus without having to produce any mechanical contact at all. When the boundary-scan technical proposal had secured the endorsement of dozens of major electronics firms, JTAG approached the IEEE in an attempt to formalize the ad hoc effort. JTAG was folded under the umbrella of PI 143, which subsequently migrated into a series of coupled, but independent, bus defi nations known as P114S. n. The furthest defined was the JTAG bus, which was designated IEEE 1143. 1. The boundary-scan proposal evolved through several draft revisions before going to ballot in August 1989. The result was an overwhelming endorsement for 1149.1, which achieved formal IEEE approval in early 1390. The goal of boundary scan is to regain lost visibility and control of designs through the inclusion of additional test logic impacting the input/output CI /CO pins of devices. Scannable flip-flops are multiplexed onto the IC functional data paths, allowing signals to be observed or to be brought io a known state via a four- wire interface. 1149.1 standardizes the four -wire interface to ensure interoperability of devices from xiiimultiple vendors Cthat Is» one scan through a Motorola part to access logic in a TI partD. 114-9. 1 -compliant parts can sample or drive their I/O pins to support testing of both the board and the ICs. In an external test mode, the outputs of a device are controlled to desired states while the inputs of neighboring devices are observed. In this context» neighboring means that two devices are interconnected by a common signal. but not the devices are physically adjacent. The external test mode allows test vectors to be scanned in and out to verify the proper interconnect of ICs on the board. This also allows the testing of nonseannable logic clusters surrounded by scannable devi ces. In an external test mode, the internal silicon is isolated from input pins while test vectors are propogated across it to the output pins. This allows testing of the device logic to the extent that adequate patterns can deviced for application from the I/O points. The 1149.1 architecture supports interfacing to internal scan and other optional test data registers to assist in testing complex ICs. The boundary scan architecture also supports a bypass mode that abbreviates the scan path to a single bit when its boundary scan registers or optional data registers are accessed. An optional device identification register may be included. Other capabilities can be accommodated easily within the boundary scan framework, such as built-in self-test, pseudo -random pattern generation, signature analysis, and more. 1149.1 devices dedicate four pins to support the industry standard bus. The 1149.1 bus consists of four wires; two of them to control scan state of the devices and the other two to transmit the serial data. This four wires are routed to all scannable devices on the board. Designers face the challenge of validating the design of their boards or ICs even in the face of high complexity. Standard processes such as visual inspection, ohming out interconnect, and verifying power and ground are complicated by the tight geometries, but the real penalty occurs during attempts to confirm functionality. A wide variety of techniques is used to debug designs, but virtually all of them require external instrumentation that connects to the board or probes the board under test. Multimeters or logic analysers are used to deter mi ne logic levels for digital signals and are necessarily constrained to observing I/O level signals. Word generators are connected to buses to apply controlled xivdata streams for test. Bus analyzers may be used to monitor states of standard bus protocols» and in-circuit emulators allow control and debug of microprocessor -based designs. Reliance on these tried -and -true instruments has two disadvantages in the light of advanced packaging techniques. Firstly» tight geometries and high-speed signals are not amenable to probing and clipping. Engineers and technicians can not probe fine-pitch designs reliably unless techniques such as stagger pads are used. Frequently, key signals are embedded within the internal logic of a device» inaccessible to contact-dependent instruments. High speed signals» such as processor signals present in emulator cables» are subject to cross talk and gl itching because of the length and layout of the cables. Secondly» design validation often requires monitoring of the design in unique environments» such as in the end -use environment or in temperature chambers. This usually requires the electronic subsystem to be closed up where access is limited to connectors on the chassis or case. Conventional instruments cannot be used to probe the design. In these cases» the visibility and control permitted by scannable designs offer alternative techniques for logic validation. Texas Instruments developed a system-level test bed using the 1149.1 architecture across four printed wiring boards CPWBs3»and using the scan for debug and integration. Manipulation of the scan was performed using a Scan Control System CSCS3. The particular tool used for this effort is called the Advanced Support System for Emulation and Test C ASSETS. ASSET is a PC-based tool that builds a data base representation for tracking and controlling the state of the scan architecture. This allows the burden of dealing with the serial view and current state of the scan paths to be relegated to the computer. ASSET uses configuration files to determine the topology of the scan paths and interfaces to the unit under test via a controller card in the PC expansion slot. ASSET drives the 1149.1 protocol. The ideal approach to implementing the debug process to have the designer develop the debug procedures while the board being fabricated. The designer most knowledgeable of the design of the board» including the partitioning of the functions within the design and how the scan architecture is implemented. The designer performed or assisted in the definition of the configuration file that identified the scan topology to the SCS. xv

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