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1200 baud FSK tümleşik modem tasarımı

Başlık çevirisi mevcut değil.

  1. Tez No: 75193
  2. Yazar: BARIŞ POSAT
  3. Danışmanlar: PROF. DR. UĞUR ÇİLİNGİROĞLU
  4. Tez Türü: Yüksek Lisans
  5. Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
  6. Anahtar Kelimeler: Belirtilmemiş.
  7. Yıl: 1998
  8. Dil: Türkçe
  9. Üniversite: İstanbul Teknik Üniversitesi
  10. Enstitü: Fen Bilimleri Enstitüsü
  11. Ana Bilim Dalı: Elektrik-Elektronik Mühendisliği Ana Bilim Dalı
  12. Bilim Dalı: Belirtilmemiş.
  13. Sayfa Sayısı: 143

Özet

ÖZET Bu çalışma kapsamında, CCITT V.23 standardına uygun 1200, 600, 300, 150 ve 75 bit /s hızlarında modülasyon, demodülasyon ve filtreleme işlemlerini yerine ge tiren bir modem tasarımı gerçekleştirilmiştir. Tasarım ağırlıklı olarak anahtarlı kapasite yaklaşımıyla gerçekleştirilen filtre ve analog işlem bloklarından oluşmak tadır. Analog devrelerle birlikte, zamanlama, kontrol ve işaret işleme amacıyla di jital devrelerden de yararlanılmıştır. Tasarımın, AMS çift-poly, çift-metal 0.8um CMOS prosesi kullanılarak tümleştirilmesi amaçlanmaktadır.

Özet (Çeviri)

SUMMARY This work involves the design of an integrated FSK modem, performing modu lation, demodulation and filtering tasks related to 1200, 600, 300, 150 and 75 bit/s operation in compliance with CCITT V.23 standart. Most of the integrated circuit consists of switched-capasitor filters and analog signal processing blocks. Together with analog circuits, digital circuits were also involved in the design to implement timing, control and signal-processing requirements. The design is going to be prototyped using AMS double-poly, double-metal 0.8um CMOS process. Square- wave digital data contain an infinite spectrum of odd harmonics at a rela tively high amplitude level. Hence, square waves would not be suitable for trans mission over band limited channels because of low- and high-frequency harmonic content. This digital waveform must be modulated to a suitable carrier frequency and then filtered to meet bandwidth requirements prior to transmission over the channel. The baseband information requires to be converted into a passband signal be tween 300 and 3400 Hz in order to be suitable for transmission and reception over the bandpass characteristic of voice-band telecommunication channels like telephone lines. This spectrum transformation or conversion, called modulation- demodulation is performed by the modem. This work focuses upon the implementation of a modem capable of generating and receiving binary FSK (frequency-shift-keyed) carriers according to CCITT V.23 standard. CCITT V.23 standard partitions the telephone line spectrum into an upper and a lower channel. The upper channel supports data rates of up to 1200 bps for normal mode operation and up to 600 bps for fall-back mode opera tion, whereas the lower channel is only able process up to 75 bps. This frequency division multiplexing scheme allows the modem to work in simplex, halt-dublex or asymmetrical full-dublex modes over 2-wire lines. The two main sections of the design can be distinguished as the transmitter and receiver. The block diagram of the transmitter is shown in Figure 1. The di gital part of the transmitter, called the modulator is in charge of generating a phase continuous frequency modulated clock at 16 times the carrier frequency xiProgrammable Attenuator TXA GAIN Figure 1 Block diagram of the transmitter which is converted into a sinusoidal carrier by the sine-wave generator and fil tered and shaped by the following low-pass switched-capacitor filter (SC TXF) and active-RC smoothing filter (SMF). These filters are required in order to reject components falling into the frequencies above the telephone bandwidth. These frequency components are sidebands caused by the modulation process, the image spectrum around switched-capacitor clock and its multiples, and dis tortion components produced by sine-wave generator. The voltage-controled-oscillation task of the modulator is implemented by a di gital circuit comprise of 164 standard-cells. The 16 times the output carrier clock produced by the modulator is fed into a D/A convertor followed by a low-pass filter. The conversion task is implemented by a capacitor array which changes the gain of the following SC low-pass filter under digital control without affecting its frequency response. This block can also be thought of as being a switched- capacitor circuit performing the multiplication between the single 1.2 V reference voltage and a regularly sampled sine wave stored in the D/A capacitor array. Due to the symmetry of the sine function, only four capacitors representing the samp led values at 22.5° intervals with the first sample taken at 11.25° are required. This sine-weighted capacitor array achieves lower distortion than binary- weighted D/A array, assuming the same capacitor ratio errors. The possitive and negative cycles are obtained by connecting the voltage reference to the noninverting or inverting input of the array, respectively. This scheme has the advantage that it does not generate even harmonics due to the fact that both half cycles are built by the same capacitors and voltage reference, thereby guaranteeing a symmetric sine wave construction even with a single polarity reference. Moreover, the odd harmonics are also minimized because of the symmetry in building the successive quadrants. Due to the different nonmultiple carriers that the modem must generate, the third order low-pass filter clock is chosen to be much higher than the maximum frequency reconstructed. In this case a 192 kHz fixed clock is used. The output of xthe switched-capacitor low-pass filter is further smoothed out by a second-order Sallen-Key active stage which is followed by an output power amplifier utilized in unity-gain configuration. The block diagram of the receiver is shown in Figure 2. The receiver amplifies the 0/ - 48 dBm input signal by the programmable amplifier stage whose gain is assigned by an automatic-gain-controler. The amplified signal is first filtered through an antialiasing filter stage and its frequency spectrum is limited so that its frequency components at and above the sampling frequency of the first switched- capacitor stage are attenuated more than 40 dB, to minimize the effect of noise aliasing in the sampling process. The band limited signal is then filtered by one of the two switched-capacitor bandpass channel-filters, i.e. RXFl and RXF2. RXFl is used for the 1200 bps and 600 bps input signals transmitted through the upper- channel, whereas RXF2 is used for the 75 bps lower-channel operation. RXFl channel filter not only increases the signal-to-noise ratio before final demodulation to improve bit error rate performance, but it also includes an optional group-delay equalizer for a typical channel in use to minimize inter symbol interference. The demodulator is probably the most critical section of the modem. It is where the final conversion to baseband occurs and thus determines to a high degree the resulting bit error rate performance of the modem. There are several different types of demodulation schemes which can be used. For this particular design the zero- or axis-crossing demodulator was chosen because it gives the best perfor mance in the presence of Gaussian noise. This is a phase incoherent detector wherein the instantaneous frequency of the incoming carrier is determined by co unting the number of the its zero crossing per unit time. That is why it is crucial for this detector to have a precise and high-performance front-end hard limiter that can deliver low-jitter zero crossings even for minimum level input carriers. This is required to avoid having a signal level dependent system performance. Before the demodulation the signal is processed by a level comparator that per forms the hard-limiting and carrier-detection and automatic gain control related level comparison functions. This hard limiter removes any amplitude modulation from the incoming carrier, preserving the zero crossing information used by the demodulator where the final conversion to baseband occurs. The extracted le vel information related to the carrier-detection is then digitally integrated and processed by a counter logic block configured as in-band energy detector with a digital delay that monitors the carrier level while providing protection against signal propouts. In the event that the carrier falls below the input refered thres hold of -48 dBm, the carrier-detector block is responsible for clamping the CD xiiiFigure 2 Block diagram of the receiver xivoutput to logic“0”. The optional automatic gain control related level information extracted by the level comprator is processed in the same manner and if the signal falls below the input refered threshold of - 27dBm the high gain level of 20 dB is assigned to the programmable amplifier, whereas for signal levels exceeding the input refered threshold of -23 dBm, the low gain level of 6 dB is used. The last blocks of the receiver, refered as PDF and slicer are basically used as a zero crossing detector that filters and slices the output of the digital monostable, called pulse generator that is designed to trigger on both the positive and the negative edges of the hard-limited signal, thus recovering the digital baseband information TXD. The hard-limited signal is digitally differentiated and rectified in order to create a pulse every time the carrier crosses zero. The zero crossing information is used to load a down counter to create a pulse of fixed duration. In essence, the the circuit called pulse generator can be viewed as a digital monostable. As a result, input frequency changes are translated into a rectangular waveform with a va riable duty cycle. This creates a baseband component proportional to the input frequency, which can be recovered by low-pass filtering. Therefore, a fifth order switched-capacitor low-pass filter follows, whose amplitude characteristic is app roximately equal to a full-raised cosine function with linear phase that minimizes intersymbol interference. The demodulator is clock and logic programmable in order to accommodate the different baud rates handled by the modem. In parti cular, at 1200 bauds a 384 kHz sampling clock is used to position the -3 dB cutoff frequency at 438 Hz, whereas at 75 bauds the clock becomes 12 kHz resulting in the -3 dB point at 27.4 Hz. Finally, the titer output is sliced by a comparator to produce the received digital data. Due to the filter and comparator offset voltages, excessive bias distortion would appear on the receive data if provisions were not made. Thus, offset cancelation techniques were utilized in the filter and comparator design to reduce the offset component below an exceptable value. The implementation contains 41 opams, 2 comparators 24 switched-capacitor po les, and 4 continuous poles. The FSK modem is integrated together with a GMSK modem and the die size related to the FSK modem circuitry is approximately 25 mm2. The expected power dissipation is about 75 mW. However, by external control the modem can be placed into a power-down mode in which it consumes less than 100 uW. xv

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